Research and Application of All Digital Phase-Locked Loop

The structure of an all digital phase-locked loop technology, ADPLL, is proposed in this paper. And the digital phase detector, digital filter loops and digital-controlled oscillators are gradually analyzed. The time order graphs of all modules are presented. In the way of linear approximation, the first-order and second-order mathematic models of ADPLL are given, as well as the control methods. The feasibility of the ADPLL is proved by simulation. Finally the ADPLL, miss-lock detector and scanning generator circuits are assembled in the FPGA are applied in an inductive heating system. This new ADPLL simplifies the structure of the control system. And the reliability is improved.

[1]  Win Chaivipas,et al.  Analysis and Design of Direct Reference Feed-Forward Compensation for Fast-Settling All-Digital Phase-Locked Loop , 2007, IEICE Trans. Electron..

[2]  Christian Vogel,et al.  Improved lock-time in all-digital phase-locked loops due to binary search acquisition , 2008, 2008 15th IEEE International Conference on Electronics, Circuits and Systems.

[3]  Barruquer Moner IX. References , 1971 .

[4]  Poras T. Balsara,et al.  Phase-domain all-digital phase-locked loop , 2005, IEEE Transactions on Circuits and Systems II: Express Briefs.