An optimal method for bottleneck station short-term Scheduling in wafer fabrication line with nonzero initial state

This paper presents initial results of a research in the short-term optimal scheduling on the photolithography station in wafer fabrication, which usually acts as a bottleneck station with multiple machines. It is desirable to minimize tardiness without loss the bottleneck utilization while today's wafer fabs are striving to maximize on delivery to their customers. Computational efficiency is one of the major challenges of applying short-term optimal scheduling of a wafer fab. This research adopts a scheduling policy that optimal scheduling for the heavily loaded bottleneck with an ant colony optimization (ACO) technique and heuristic rules for other lightly-workload stations, taking account of information of both online WIP and new release lots in scheduling horizon, which yields superior results with modest computational effort and enable the practical use of the optimal method.

[1]  Young Hoon Lee,et al.  Experimental study on input and bottleneck scheduling for a semiconductor fabrication line , 2002 .

[2]  YOUNG HOON LEE,et al.  Experimental study on input and bottleneck scheduling for a semiconductor fabrication line , 2002 .

[3]  Don T. Phillips,et al.  A state-of-the-art survey of dispatching rules for manufacturing job shop operations , 1982 .

[4]  Fei Qiao,et al.  A Lot Dispatching Strategy Integrating WIP Management and Wafer Start Control , 2007, IEEE Transactions on Automation Science and Engineering.

[5]  Reha Uzsoy,et al.  Measures of subproblem criticality in decomposition algorithms for shop scheduling , 2003 .

[6]  Jiang Zhibin,et al.  An approach of dynamic bottleneck machine dispatching for semiconductor wafer fab , 2007, 2007 International Symposium on Semiconductor Manufacturing.

[7]  R. Bixby,et al.  Short-Interval Detailed Production Scheduling in 300mm Semiconductor Manufacturing using Mixed Integer and Constraint Programming , 2006, The 17th Annual SEMI/IEEE ASMC 2006 Conference.

[8]  N. Govind,et al.  Operations Management in Automated Semiconductor Manufacturing With Integrated Targeting, Near Real-Time Scheduling, and Dispatching , 2008, IEEE Transactions on Semiconductor Manufacturing.

[9]  Kenneth Fordyce,et al.  Technology that upsets the social order — a paradigm shift in assigning lots to tools in a wafer fabricator — the transition from rules to optimization , 2008, 2008 Winter Simulation Conference.

[10]  Salvatore Cavalieri,et al.  A genetic algorithm for job-shop scheduling in a semiconductor manufacturing system , 1999, IECON'99. Conference Proceedings. 25th Annual Conference of the IEEE Industrial Electronics Society (Cat. No.99CH37029).

[11]  Reha Uzsoy,et al.  Performance of decomposition procedures for job shop scheduling problems with bottleneck machines , 2000 .

[12]  Zhou Bing-hai Real-time Scheduling of Dynamic Bottleneck Facilities of Wafer Fabrication Processes , 2008 .

[13]  Reha Uzsoy,et al.  Observations on the interactions among deadlock avoidance policies and dispatching rules in automated manufacturing systems , 2003 .

[14]  Lawrence M. Wein,et al.  Scheduling semiconductor wafer fabrication , 1988 .

[15]  Han-Pang Huang,et al.  A New Approach to On-Line Rescheduling for a Semiconductor Foundry Fab , 2006, 2006 IEEE International Conference on Systems, Man and Cybernetics.

[16]  Wu Qi-di Research on dynamic dispatching rule for semiconductor wafer fabrication , 2004 .

[17]  John W. Fowler,et al.  Genetic algorithm based scheduling of parallel batch machines with incompatible job families to minimize total weighted tardiness , 2004 .