An Area-efficient Non-uniform Filter Bank for Low Overhead Reconfiguration of Multi-standard Software Radio Channelizers

The channelizer in a software defined radio (SDR) base station extracts individual radio channels from the digitized wideband input signal at a very high sampling rate. The base station channelizer must be able to simultaneously extract multiple channels of non-uniform bandwidths corresponding to channel bandwidths of different communication standards. Reconfigurability and low complexity are the two key requirements in the SDR channelizer. A new reconfigurable filter bank (FB) architecture based on interpolation and masking technique for SDR channelizers is proposed in this paper. The proposed FB can be used for obtaining very narrow passband channels with extremely low complexity. Using a cascaded structure of the proposed FB, it is possible to extract channels of fractional passband widths by changing the interpolation factor. Design example shows that the proposed FB offers complexity reduction of 84% over the conventional per-channel (PC) approach. The proposed FB has been implemented and tested on Xilinx Virtex 2v3000ff1152-4 FPGA. Implementation results show that the proposed FB offers area reduction of 48.37%, speed improvement of 52.7% and power reduction of 75.9% over the PC approach.

[1]  A.A. Abidi,et al.  The Path to the Software-Defined Radio Receiver , 2007, IEEE Journal of Solid-State Circuits.

[2]  Tim Hentschel.  Channelization for software defined base-stations , 2002, Ann. des Télécommunications.

[3]  Young Hwan Lim.  A digital filter bank for digital audio systems , 1986 .

[4]  Yoan Shin,et al.  SDR-based digital channelizer/de-channelizer for multiple CDMA signals , 2000, Vehicular Technology Conference Fall 2000. IEEE VTS Fall VTC2000. 52nd Vehicular Technology Conference (Cat. No.00CH37152).

[5]  Shing-Chow Chan,et al.  A multistage filterbank-based channelizer and its multiplier-less realization , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[6]  Yong Ching Lim,et al.  Fast filter bank (FFB) , 1992 .

[7]  Yong Ching Lim,et al.  Analysis and optimum design of the FFB , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

[8]  N. Spencer.  An overview of digital telephony standards , 1998 .

[9]  Yong Ching Lim,et al.  Frequency-response masking approach for the synthesis of sharp linear phase digital filters , 1986 .

[10]  Mahmut T. Kandemir,et al.  Leakage Current: Moore's Law Meets Static Power , 2003, Computer.

[11]  Lee Jun Wei,et al.  A flexible and efficient sharp filter bank architecture for variable bandwidth systems , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[12]  Ravinder David Koilpillai,et al.  Software radio issues in cellular base stations , 1999, IEEE J. Sel. Areas Commun..

[13]  Chiew Tong Lau,et al.  A reconfigurable multi-standard channelizer using QMF trees for software radio receivers , 2003, 14th IEEE Proceedings on Personal, Indoor and Mobile Radio Communications, 2003. PIMRC 2003..

[14]  MitolaJ..  Software radio architecture , 1999 .

[15]  R. Mahesh,et al.  A new low complexity reconfigurable filter bank architecture for software radio receivers based on interpolation and masking technique , 2007, 2007 6th International Conference on Information, Communications & Signal Processing.

[16]  A. Prasad Vinod,et al.  Reconfigurable Frequency Response Masking Filters for Software Radio Channelization , 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.

[17]  Gerard J. M. Smit,et al.  Towards Software Defined Radios Using Coarse-Grained Reconfigurable Hardware , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[18]  P. McAndrew,et al.  Digital signal processing aspects of software definable radios , 1998 .

[19]  Gordon L. Stüber,et al.  Efficient wideband channelizer for software radio systems using modulated PR filterbanks , 2004, IEEE Transactions on Signal Processing.

[20]  Shing-Chow Chan,et al.  Design and Complexity Optimization of a New Digital IF for Software Radio Receivers With Prescribed Output Accuracy , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[21]  Navid Lashkarian,et al.  Reconfigurable Digital Front-End Hardware for Wireless Base-Station Transmitters: Analysis, Design and FPGA Implementation , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[22]  J. W. Lee,et al.  Efficient implementation of real filter banks using frequency response masking techniques , 2002, Asia-Pacific Conference on Circuits and Systems.

[23]  Ming Jian,et al.  An efficient IF architecture for dual-mode GSM/W-CDMA receiver of a software radio , 1999, 1999 IEEE International Workshop on Mobile Multimedia Communications (MoMuC'99) (Cat. No.99EX384).