An approach to instruction scheduling at the processor architecture level for optimizing embedded software

The optimization problem of embedded systems and embedded software plays an important role. The optimization based on instruction scheduling has not been researched commonly and it focused primarily on optimizing the power consumption. Most studies have not considered the architecture and configurable character of modern processors. Therefore, in this paper, we propose and develop a new instruction scheduling method to optimize the performance and the power consumption for both pipeline and superscalar architecture. In order to optimize energy, we build a power consumption table of instructions and apply the genetic algorithm to arrange instructions of an assembly program. To optimize the performance of embedded software, we analyze the pipeline and superscalar architecture of a processor to construct performance evaluation functions under an instruction chain. Based on the performance evaluation function, we also apply the genetic algorithm to find the execution order of instructions having the best performance corresponding to each type of processor architectures.