11.4 A 1.5mW 68dB SNDR 80MS/s 2× interleaved SAR-assisted pipelined ADC in 28nm CMOS

The resolution and sampling speed of recently reported SAR ADCs have increased to 11+ ENOB at 50 to 100MS/s [1,2]; however, power efficiency has unfortunately suffered when compared to lower-resolution, lower-speed ADCs. This design targets the same high speed and resolution while simultaneously achieving power efficiency previously associated only with low-speed, low-resolution ADCs. Furthermore, the power reported includes the consumption from the active reference generator, clock generator and encoder (since this is an industrial SoC), differentiating it from the majority of reported SAR ADCs. A dynamic residue amplifier with excellent noise-filtering properties, embedded in a pipelined architecture, is a key power-saving technique. In addition, an energy-efficient switched-capacitor (SC) DAC is obtained by using a small fraction of the total DAC capacitance during the initial SAR steps. The realized Walden FOM is 9.1fJ/conv-step while the Schreier FoM is 172.3dB, currently the highest reported number to date for sampling speeds greater than 0.1Ms/s, based on the extensive list of recent data converters compiled in [3].

[1]  Jan Craninckx,et al.  A 1.7 mW 11b 250 MS/s 2-Times Interleaved Fully Dynamic Pipelined SAR ADC in 40 nm Digital CMOS , 2012, IEEE Journal of Solid-State Circuits.

[2]  Eitake Ibaragi,et al.  A 14b 80 MS/s SAR ADC With 73.6 dB SNDR in 65 nm CMOS , 2013, IEEE Journal of Solid-State Circuits.

[3]  Eitake Ibaragi,et al.  A 14b 80MS/s SAR ADC with 73.6dB SNDR in 65nm CMOS , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[4]  Takashi Morie,et al.  A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR enhancement techniques utilizing noise , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[5]  Brian P. Ginsburg,et al.  An energy-efficient charge recycling approach for a SAR converter with capacitive DAC , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[6]  Jan Craninckx,et al.  A 1.7mW 11b 250MS/s 2× interleaved fully dynamic pipelined SAR ADC in 40nm digital CMOS , 2012, 2012 IEEE International Solid-State Circuits Conference.

[7]  Akira Matsuzawa,et al.  A 15.5 dB, wide signal swing, dynamic amplifier using a common-mode voltage detection technique , 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

[8]  Soon-Jyh Chang,et al.  A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure , 2010, IEEE Journal of Solid-State Circuits.