A Hierarchical Test Generation Approach Using Program Slicing Techniques on Hardware Description Languages

Sequential Automatic Test Pattern Generation is extremely computation intensive and produces acceptable results only on relatively small designs. Hierarchical approaches that target one module at a time and use ad-hoc abstractions for the rest of the design, have shown promising results in reducing the test generation complexity. This paper develops an elegant theoretical basis, based on program slicing, for hierarchical test generation. The technique to systematically obtain a “constraint slice” for each embedded module under test within a design, is described in detail. The technique has been incorporated in an automated tool for Verilog designs, and results on large benchmark circuits show the significant benefits of the approach.