Optimized Synthesis of Self-Testable Finite State Machines (FSM) Using BIST-PST Structures in Altera Structures

The testing of PCBs containig ASICs, e.g., Altera FPGA is an important problem which needs consideration. One of the ideas of solving this problem is using BIST architecture for each ASIC. With the use of built-in testers, the additional cost, in the form of overhead of macrocells is added. A certain idea of built-in tester structures is BIST-PST [1]. The disadventage of this idea is, that the FSM memory block in form of MISR with a given characteristic polynomial may be realized only in form of: IE-MISR and EE-MISR. In our paper, the new kind of MISR registers consisting of D and T flip-flops has been used in BIST-PST. They make it possible for a given characteristic polynomial to achieve a wide range of possible realizations of MISR type memory block, ranging from tens to thousands. In effect, it is possible to choose the minimal excitation function saving a considerable number of Altera FPGA macrocells.