Controllable readout circuit for indium gallium arsenide photodiode array applications

This study presents a controllable integration time readout integrated circuit (ROIC) with a 32 by 32 indium gallium arsenide (InGaAs) detector array. This ROIC is designed for InGaAs photodiode (PD) array detectors to operate at low input current and is suitable for the focal plane array (FPA) in near infrared (NIR) field. The integration time of this ROIC can be controlled by an external clock pulse, and is adjustable from 0.5 s to infinity by varying the light intensity. Moreover, the pre-stage of ROIC is based on the buffer gate modulation input (BGMI) architecture with differential structure and a double delta sampling (DDS) circuit, providing better sensitivity, a wider dynamic range, a higher injection efficiency and reduced noise. Further, because this ROIC is built into a sample-and-hold circuit in the unit cell, it can operate in the full frame snapshot mode. The proposed ROIC has 1024 pixels and a 30-mum pixel pitch. It is implemented using Taiwan Semiconductor Manufacturing Company (TSMC) 0.35 mum Complementary Metal-Oxide-Semiconductor (CMOS) process with a 5-V power supply. The output swing is over 2.2 V. It has 5 non-linearity, 91.559 mW chip power dissipation and a chip area of 1.628 2.341 mm 2 without pads.