In this study, we propose a systematic method to separate the hole trapping from measured V1 shift, thus giving the ideal interface trap generation behavior without measurement disturbance. Three stages of interface trap generation have been illustrated with the analytical H-H2 NBTI reaction-diffusion model, and the hole trapping has also been verified with its voltage-enhanced and temperature-insensitive properties. Finally, the PMOS device lifetime extrapolation without considering the hole trapping might lead to significant lifetime overestimation.