Wykorzystanie charakterystyki adresowej w transparentnym testowaniu pamięci RAM

[1]  Tom Chen,et al.  Design of a self-testing and self-repairing structure for highly hierarchical ultra-large capacity memory chips , 1993, IEEE Trans. Very Large Scale Integr. Syst..

[2]  Jacob Savir,et al.  Built In Test for VLSI: Pseudorandom Techniques , 1987 .

[3]  Hans-Joachim Wunderlich,et al.  Self-adjusting output data compression: An efficient BIST technique for RAMs , 1998, Proceedings Design, Automation and Test in Europe.

[4]  R. Rajsuman.  Rambist builder: a methodology for automatic built-in self-test design of embedded rams , 1996, IEEE International Workshop on Memory Technology, Design and Testing,.

[5]  Sunil Jain,et al.  Built-in Self Testing of Embedded Memories , 1986, IEEE Design & Test of Computers.

[6]  R. Dekker,et al.  Realistic built-in self-test for static RAMs , 1989, IEEE Design & Test of Computers.

[7]  A. J. van de Goor,et al.  Testing Semiconductor Memories: Theory and Practice , 1998 .

[8]  Michael Nicolaidis,et al.  TRANSPARENT BIST FOR RAMS , 1992, Proceedings International Test Conference 1992.

[9]  Kewal K. Saluja,et al.  A Novel Approach for Testing Memories Using a Built-In Self Testing Technique , 1986, International Test Conference.

[10]  Bruce F. Cockburn,et al.  Synthesized transparent BIST for detecting scrambled pattern-sensitive faults in RAMs , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[11]  V. K. Agarwal,et al.  Built-in self-diagnosis for repairable embedded RAMs , 1993, IEEE Design & Test of Computers.