Evaluation of TSV and micro-bump probing for wide I/O testing

Practical silicon stacking requires pre-tested dies, but contact probing of TSV interconnects requires much higher density, lower probing forces, and lower cost per pin than conventional probe cards have achieved. This paper examines a cost-effective, lithographic-based MEMS probe card technology that is suitable for probing 40µm pitch arrays, and scalable to finer pitches. Initial mechanical and electrical results are presented, demonstrating the feasibility of probing large arrays at 1 gram-force per tip with very low pad damage, so as not to impair downstream bonding or other processing steps.

[1]  Hsien-Hsin S. Lee,et al.  Test Challenges for 3D Integrated Circuits , 2009, IEEE Design & Test of Computers.

[2]  Bart Swinnen,et al.  3D System Integration Technologies , 2007, ICICDT 2007.

[3]  Young-Hyun Jun,et al.  A 1.2V 12.8GB/s 2Gb mobile Wide-I/O DRAM with 4×128 I/Os using TSV-based stacking , 2011, 2011 IEEE International Solid-State Circuits Conference.

[4]  Peter Ramm,et al.  Handbook of 3D integration : technology and applications of 3D integrated circuits , 2012 .

[5]  Yervant Zorian,et al.  Testing 3D chips containing through-silicon vias , 2009, 2009 International Test Conference.

[6]  Young-Hyun Jun,et al.  A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 $\times$ 128 I/Os Using TSV Based Stacking , 2011, IEEE Journal of Solid-State Circuits.

[7]  Robert S. Patti,et al.  Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs , 2006, Proceedings of the IEEE.

[8]  Erik Jan Marinissen,et al.  Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base , 2011, 2011 IEEE International Test Conference.

[9]  A. Jourdain,et al.  3D stacked IC demonstration using a through Silicon Via First approach , 2008, 2008 IEEE International Electron Devices Meeting.

[10]  E. Beyne,et al.  3D integration by Cu-Cu thermo-compression bonding of extremely thinned bulk-Si die containing 10 μm pitch through-Si vias , 2006, 2006 International Electron Devices Meeting.

[11]  Kaustav Banerjee,et al.  3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration , 2001, Proc. IEEE.

[12]  K. Saban Xilinx Stacked Silicon Interconnect Technology Delivers Breakthrough FPGA Capacity , Bandwidth , and Power Efficiency , 2009 .

[13]  Erik Jan Marinissen,et al.  Test Cost Analysis for 3D Die-to-Wafer Stacking , 2010, 2010 19th IEEE Asian Test Symposium.