Input Vector Monitoring Concurrent BIST Architecture Using SRAM Cells

Input vector monitoring concurrent built-in self test (BIST) schemes perform testing during the normal operation of the circuit without imposing a need to set the circuit offline to perform the test. These schemes are evaluated based on the hardware overhead and the concurrent test latency (CTL), i.e., the time required for the test to complete, whereas the circuit operates normally. In this brief, we present a novel input vector monitoring concurrent BIST scheme, which is based on the idea of monitoring a set (called window) of vectors reaching the circuit inputs during normal operation, and the use of a static-RAM-like structure to store the relative locations of the vectors that reach the circuit inputs in the examined window; the proposed scheme is shown to perform significantly better than previously proposed schemes with respect to the hardware overhead and CTL tradeoff.

[1]  Edward McCluskey,et al.  Built-In Self-Test Techniques , 1985, IEEE Design & Test of Computers.

[2]  Janusz Rajski,et al.  Test responses compaction in accumulators with rotate carry adders , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Kewal K. Saluja,et al.  A concurrent testing technique for digital circuits , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  Constantin Halatsis,et al.  A concurrent built-in self-test architecture based on a self-testing RAM , 2005, IEEE Transactions on Reliability.

[5]  Kewal K. Saluja,et al.  Theory, Analysis and Implementation of an On-LineBIST Technique , 1993 .

[6]  Hans-Joachim Wunderlich,et al.  Concurrent Self-Test with Partially Specified Patterns for Low Test Latency and Overhead , 2009, 2009 14th IEEE European Test Symposium.

[7]  Yervant Zorian,et al.  An Effective BIST Scheme for ROM's , 1992, IEEE Trans. Computers.

[8]  Yiorgos Makris,et al.  Concurrent Error Detection Methods for Asynchronous Burst-Mode Machines , 2007, IEEE Transactions on Computers.

[9]  I. Voyiatzis.  On reducing aliasing in accumulator-based compaction , 2008, 2008 3rd International Conference on Design and Technology of Integrated Systems in Nanoscale Era.

[10]  Sy-Yen Kuo,et al.  Gauss-elimination-based generation of multiple seed-polynomial pairs for LFSR , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Constantin Halatsis,et al.  A low-cost concurrent BIST scheme for increased dependability , 2005, IEEE Transactions on Dependable and Secure Computing.

[12]  C. Efstathiou,et al.  A concurrent BIST architecture based on Monitoring Square Windows , 2010, 5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era.

[13]  Yiorgos Makris,et al.  Entropy-driven parity-tree selection for low-overhead concurrent error detection in finite state machines , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.