Clock generation and distribution for intel Banias mobile microprocessor

This clock generation and distribution scheme enables Intel's first mobile-specific micro-architecture of Banias microprocessor. It employs four phase-locked loops, three of them cascaded, to generate the required clock frequencies, provide low skew and jitter and support the next-generation Intel SpeedStep/spl reg/ technology. The core clock distribution is implemented as two grids with an active continuous de-skewing mechanism. The debug capabilities of this clocking scheme provide easy observability and testing, enabling rapid time to market.

[1]  B. Bhushan,et al.  A 0.35 /spl mu/m CMOS 3-880 MHz PLL N/2 clock multiplier and distribution network with low jitter for microprocessors , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[2]  S. Tam,et al.  Clock generation and distribution for the first IA-64 microprocessor , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[3]  Nasser A. Kurd,et al.  A multigigahertz clocking scheme for the Pentium(R) 4 microprocessor , 2001, IEEE J. Solid State Circuits.