A Novel Pipeline Design for H.264 CABAC Decoding

H.264/AVC is the newest international video coding standard. This paper presents a novel hardware design for CABAC decoding in H.264/AVC. CABAC is the key innovative technology, but it brings huge challenge for high throughput implementation. The current bin decoding depends on the previous bin, which results in the long latency and limits the system performance. In this paper, the data hazards are analyzed and resolved using the algorithmic features. We present a new pipeline-based architecture using the standard look-ahead technique where the arithmetic decoding engine works in parallel with the context maintainer. An efficient finite state machine is developed to match the requirement of the pipeline controlling and the critical path is optimized for the timing. The proposed implementation can generate one bin per clock cycle at the 160-MHz working frequency.