Impact of programming mechanisms on the performance and reliability of nonvolatile memory devices based on Si nanocrystals

A nonvolatile memory based on silicon nanocrystals (nc-Si) synthesized with very-low-energy Si/sup +/ implantation is fabricated, and the memory performance under the programming/erasing of either Fowler-Nordheim (FN)/FN or channel hot electron (CHE)/FN at both room temperature and 85/spl deg/C is investigated. The CHE programming has a larger memory window, a better endurance, and a longer retention time as compared to FN programming. In addition, the CHE programming yields less stress-induced leakage current than FN programming, suggesting that it produces less damage to the gate oxide and the oxide/Si interface. Detailed discussions on the impact of the programming mechanisms are presented.

[1]  D. Ielmini,et al.  Silicon nanocrystal memories: a status update. , 2007, Journal of nanoscience and nanotechnology.

[2]  M. Perego,et al.  Silicon nanocrystal memory devices obtained by ultra-low-energy ion-beam synthesis , 2004 .

[3]  B. Eitan,et al.  Characterization of channel hot electron injection by the subthreshold slope of NROM/sup TM/ device , 2001, IEEE Electron Device Letters.

[4]  Salvatore Lombardo,et al.  Nanocrystal memories for FLASH device applications , 2004 .

[5]  William D. Brown,et al.  Nonvolatile Semiconductor Memory Technology , 1997 .

[6]  B. Eitan,et al.  NROM: A novel localized trapping, 2-bit nonvolatile memory cell , 2000, IEEE Electron Device Letters.

[7]  Sandip Tiwari,et al.  Volatile and non-volatile memories in silicon with nano-crystal storage , 1995, Proceedings of International Electron Devices Meeting.

[8]  C.T. Swift,et al.  A 6 V embedded 90 nm silicon nanocrystal nonvolatile memory , 2003, IEEE International Electron Devices Meeting 2003.

[9]  Donggun Park,et al.  Data retention characteristics of sub-100 nm NAND flash memory cells , 2003, IEEE Electron Device Letters.

[10]  Mark L. Green,et al.  Ultrathin (<4 nm) SiO2 and Si-O-N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits , 2001 .

[11]  K. Stegemann,et al.  Non-volatile memories based on Si+-implanted gate oxides , 2001 .

[12]  R. Zhang,et al.  Silicon nanocrystal memories , 2004, Proceedings. 7th International Conference on Solid-State and Integrated Circuits Technology, 2004..

[13]  B. Eitan,et al.  Investigation of channel hot electron injection by localized charge-trapping nonvolatile memory devices , 2004, IEEE Transactions on Electron Devices.

[14]  S. Lombardo,et al.  Silicon nanocrystal memories , 2004 .

[15]  S. Straub,et al.  Silicon nanocrystal based memory devices for NVM and DRAM applications , 2004 .