Parametric yield optimisation of MOS VLSI circuits based on simulated annealing and its parallel implementation

As device dimensions continuously scale down in current MOS VLSI technology, statistical tolerances of process parameters become more significant. Thus, for circuit designers, it is essential to estimate the influence of such variations on circuit performances and to optimise the circuit so that the maximum yield is obtained. This paper presents an approach for parametric yield optimisation of MOS VLSI circuits, in which both the simulated annealing and gradient algorithms are combined to improve the computational efficiency. With respect to other methods the proposed approach can be considered more general and robust. In addition, it is able to take deterministic parameters into account and to solve multiobjective problems. To improve the computational efficiency, the method has been implemented in a parallel computing machine based on an array of 16 transputers. Several examples of digital-and analog circuit design optimisation are reported to demonstrate the validity of the approach.< >