A parallel implementation of deblocking filter based on video array architecture for HEVC

Energy efficiency has become one of the most important topics in computing. High Efficiency Video Coding (HEVC) still adopts the hybrid coding framework. The blocking artifacts still exist and deblocking filter in the HEVC used to reduce the blocking artifacts. Deblocking filter can improve both the subjective and objective video quality, has lowered computational complexity and allows parallel processing. In order to increase the execution efficiency, this paper proposes a parallel implementation of deblocking filter for a 16 ×16 pixel block basis in HEVC standard based on Video Array Architecture, which is programmable and self-reconfigurable driven by energy efficiency, so as to which could achieve high compute performance at a low energy cost. According to the dependence of pixel process, the 16 × 16 pixel block is divided into two types by using 32 thin-core processing elements (TCPE). The experimental results show that the frequency is up to 153.386MHZ synthesized under an XC7Z045 FFG900-2 FPGA chip.

[1]  Tian-Sheuan Chang,et al.  A hardware-efficient deblocking filter design for HEVC , 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

[2]  Sergio Bampi,et al.  A deblocking filter hardware architecture for the high efficiency video coding standard , 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[3]  Mihir Mody,et al.  High throughput VLSI architecture supporting HEVC loop filter for Ultra HDTV , 2013, 2013 IEEE Third International Conference on Consumer Electronics ¿ Berlin (ICCE-Berlin).

[4]  Weiwei Shen,et al.  A pipelined VLSI architecture for Sample Adaptive Offset (SAO) filter and deblocking filter of HEVC , 2013, IEICE Electron. Express.

[5]  Xin Ye,et al.  A cost-efficient hardware architecture of deblocking filter in HEVC , 2014, 2014 IEEE Visual Communications and Image Processing Conference.

[6]  Satoshi Goto,et al.  A High Performance HEVC De-Blocking Filter and SAO Architecture for UHDTV Decoder , 2013, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

[7]  Minhua Zhou,et al.  HEVC Deblocking Filter , 2012, IEEE Transactions on Circuits and Systems for Video Technology.

[8]  Hong Zhang,et al.  High efficiency video coding (HEVC) based screen content coding , 2013 .

[9]  Ilker Hamzaoglu,et al.  A high performance deblocking filter hardware for High Efficiency Video Coding , 2013, 2013 23rd International Conference on Field programmable Logic and Applications.

[10]  Wei Cheng,et al.  A high-throughput HEVC deblocking filter VLSI architecture for 8k×4k application , 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

[11]  Gary J. Sullivan,et al.  Overview of the High Efficiency Video Coding (HEVC) Standard , 2012, IEEE Transactions on Circuits and Systems for Video Technology.

[12]  Weiwei Shen,et al.  A high-throughput VLSI architecture for deblocking filter in HEVC , 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).