A centralized supply voltage and local body bias-based compensation approach to mitigate within-die process variation

With the scaling of MOSFET dimensions and the enhancements introduced to boost its performance, variation in semiconductor manufacturing has increased. The manufactured designs are usually shifted from the intended operating point, degrading the parametric yield. In this paper, we partition the chip into multiple regions with localized sensors and introduce a centralized control system with region-specific bias control to mitigate the impact of within-die (WID) process variation. An algorithm for determining the minimum required global supply voltage across all the regions and optimal body-biasing voltages for the individual regions is illustrated. This system ensures the desired frequency of operation for the chip under optimal power conditions for each of the regions. Design considerations, simulation results and power-performance characteristics of this fine-grain body biasing compensation technique are presented based on simulations of the IBM 65 nm technology. This method achieves an average reduction of 7.2% in total power dissipated across process corners while bringing the critical path delay in all modules within the desired +/− 3% of nominal delay.

[1]  T. N. Vijaykumar,et al.  Distance associativity for high-performance energy-efficient non-uniform cache architectures , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..

[2]  Tom W. Chen,et al.  A low cost individual-well adaptive body bias (IWABB) scheme for leakage power reduction and performance enhancement in the presence of intra-die variations , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[3]  Sachin S. Sapatnekar,et al.  Body Bias Voltage Computations for Process and Temperature Compensation , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[4]  Tom W. Chen,et al.  Post Silicon Power/Performance Optimization in the Presence of Process Variations Using Individual Well-Adaptive Body Biasing , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[5]  Makoto Nagata,et al.  Substrate-noise and random-fluctuations reduction with self-adjusted forward body bias , 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

[6]  S SapatnekarSachin,et al.  Body bias voltage computations for process and temperature compensation , 2008 .

[7]  Ching-Te Chuang,et al.  On-Chip Process Variation Detection and Compensation Using Delay and Slew-Rate Monitoring Circuits , 2008, ISQED 2008.

[8]  Doug Burger,et al.  An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches , 2002, ASPLOS X.

[9]  S. Borkar,et al.  Dynamic-sleep transistor and body bias for active leakage power control of microprocessors , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[10]  G. Ono,et al.  Threshold-voltage balance for minimum supply operation , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

[11]  E. Alon,et al.  The implementation of a 2-core, multi-threaded itanium family processor , 2006, IEEE Journal of Solid-State Circuits.

[12]  David Blaauw,et al.  Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations , 2003, ICCAD 2003.

[13]  Masayuki Miyazaki,et al.  Threshold-voltage balance for minimum supply operation [LV CMOS chips] , 2003, IEEE J. Solid State Circuits.

[14]  James Tschanz,et al.  Adaptive circuit techniques to minimize variation impacts on microprocessor performance and power , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[15]  Eric S. Fetzer.  Using Adaptive Circuits to Mitigate Process Variations in a Microprocessor Design , 2006, IEEE Design & Test of Computers.

[16]  David Blaauw,et al.  Statistical Analysis and Optimization for VLSI: Timing and Power , 2005, Series on Integrated Circuits and Systems.

[17]  Mark Horowitz,et al.  Energy dissipation in general purpose microprocessors , 1996, IEEE J. Solid State Circuits.

[18]  S. Naffziger,et al.  The implementation of a 2-core, multi-threaded Itanium/spl reg/ family processor , 2005, 2005 International Conference on Integrated Circuit Design and Technology, 2005. ICICDT 2005..

[19]  Lawrence T. Clark,et al.  An embedded 32-b microprocessor core for low-power and high-performance applications , 2001 .

[20]  Ching-Te Chuang,et al.  On-Chip Process Variation Detection and Compensation Using Delay and Slew-Rate Monitoring Circuits , 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

[21]  Masayuki Miyazaki,et al.  Optimum threshold-voltage tuning for low-power, high-performance microprocessor , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[22]  Josep Torrellas,et al.  Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).

[23]  T. Chen,et al.  Comparison of adaptive body bias (ABB) and adaptive supply voltage (ASV) for improving delay and leakage under the presence of process variation , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[24]  T. N. Vijaykumar,et al.  Optimizing Replication, Communication, and Capacity Allocation in CMPs , 2005, ISCA 2005.

[25]  Vivek De,et al.  Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[26]  Vivek De,et al.  Forward body bias for microprocessors in 130nm technology generation and beyond , 2002, VLSIC 2002.

[27]  Zeshan Chishti,et al.  Optimizing replication, communication, and capacity allocation in CMPs , 2005, 32nd International Symposium on Computer Architecture (ISCA'05).

[28]  Kevin J. Nowka,et al.  Parametric yield analysis and constrained-based supply voltage optimization , 2005, Sixth international symposium on quality electronic design (isqed'05).