On the computation of the ranges of detected delay fault sizes

Existing methodologies for determining gate delay fault coverages through the computation of detected fault sizes are shown to have certain deficiencies. A method is proposed to determine all the possible ranges of detected fault sizes, thereby maximizing the fault coverage of a given test sequence. The ultimate goal of ensuring that the coverage for a particular fault extends up to the actual circuit slack is explored, and methods are given to achieve such coverages wherever possible. Results of experiments performed to evaluate the practical benefits of the proposed methods are reported.<<ETX>>

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