Energy-Performance Trade-offs on Energy-Constrained Devices with Multi-component DVFS

Battery lifetime continues to be a top complaint about smart phones. Dynamic voltage and frequency scaling (DVFS) has existed for mobile device CPUs for some time, and provides a trade off between energy and performance. Dynamic frequency scaling is beginning to be applied to memory as well to make more energy-performance tradeoffs possible. We present the first characterization of the behavior of the optimal frequency settings of workloads running both, under energy constraints and on systems capable of CPU DVFS and memory DFS, an environment representative of next-generation mobile devices. Our results show that continuously using the optimal frequency settings results in a large number of frequency transitions which end up hurting performance. However, by permitting a small loss in performance, transition overhead can be reduced and end-to-end performance and energy consumption improved. We introduce the idea of inefficiency as a way of constraining task energy consumption relative to the most energy-efficient settings, and characterize the performance of multiple workloads running under different inefficiency settings. Overall our results have multiple implications for next-generation mobile devices exposing multiple energy-performance tradeoffs.

[1]  Ricardo Bianchini,et al.  Limiting the power consumption of main memory , 2007, ISCA '07.

[2]  Alvin R. Lebeck,et al.  Power aware page allocation , 2000, SIGP.

[3]  Amin Vahdat,et al.  ECOSystem: managing energy as a first class operating system resource , 2002, ASPLOS X.

[4]  Qingyuan Deng,et al.  MemScale: active low-power modes for main memory , 2011, ASPLOS XVI.

[5]  Mahmut T. Kandemir,et al.  Domain knowledge based energy management in handhelds , 2015, 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA).

[6]  Christoforos E. Kozyrakis,et al.  Towards energy-proportional datacenter memory with mobile DRAM , 2012, 2012 39th Annual International Symposium on Computer Architecture (ISCA).

[7]  David W. Nellans,et al.  Micro-pages: increasing DRAM efficiency with locality-aware data placement , 2010, ASPLOS XV.

[8]  Thomas F. Wenisch,et al.  CoScale: Coordinating CPU and Memory System DVFS in Server Systems , 2012, 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture.

[9]  Thomas F. Wenisch,et al.  MultiScale: memory system DVFS with multiple memory controllers , 2012, ISLPED '12.

[10]  Chris Fallin,et al.  Memory power management via dynamic voltage/frequency scaling , 2011, ICAC '11.

[11]  Margaret Martonosi,et al.  Long-term workload phases: duration predictions and applications to DVFS , 2005, IEEE Micro.

[12]  Margaret Martonosi,et al.  Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors , 2009, ISCA '09.

[13]  Anantha Chandrakasan,et al.  Full-chip sub-threshold leakage power prediction model for sub-0.18 μm CMOS , 2002, ISLPED '02.

[14]  Anantha Chandrakasan,et al.  Full-chip subthreshold leakage power prediction model for sub-0 . 18 m CMOS , 2002 .

[15]  Bishop Brock,et al.  Introducing the Adaptive Energy Management Features of the Power7 Chip , 2011, IEEE Micro.

[16]  Xiaodong Li,et al.  Cross-component energy management: Joint adaptation of processor and memory , 2007, TACO.

[17]  Gu-Yeon Wei,et al.  Thread motion: fine-grained power management for multi-core systems , 2009, ISCA '09.

[18]  Gu-Yeon Wei,et al.  A Fully-Integrated 3-Level DC-DC Converter for Nanosecond-Scale DVFS , 2012, IEEE Journal of Solid-State Circuits.

[19]  Zhao Zhang,et al.  Decoupled DIMM: building high-bandwidth memory system using low-speed DRAM devices , 2009, ISCA '09.

[20]  Philip Levis,et al.  Apprehending joule thieves with cinder , 2009, MobiHeld '09.

[21]  Margaret Martonosi,et al.  An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget , 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).

[22]  Jung Ho Ahn,et al.  McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[23]  Sally A. McKee,et al.  Machine learning based online performance prediction for runtime parallelization and task scheduling , 2009, 2009 IEEE International Symposium on Performance Analysis of Systems and Software.

[24]  Norman P. Jouppi,et al.  CACTI: an enhanced cache access and cycle time model , 1996, IEEE J. Solid State Circuits.

[25]  Mark Hempstead,et al.  The Case for Power-Agile Computing , 2011, HotOS.

[26]  Margaret Martonosi,et al.  Wattch: a framework for architectural-level power analysis and optimizations , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).

[27]  Brad Calder,et al.  Selecting software phase markers with code structure analysis , 2006, International Symposium on Code Generation and Optimization (CGO'06).

[28]  Somayeh Sardashti,et al.  The gem5 simulator , 2011, CARN.

[29]  Xue Li,et al.  Coordinating processor and main memory for efficientserver power control , 2011, ICS '11.

[30]  Karthick Rajamani,et al.  A performance-conserving approach for reducing peak power consumption in server systems , 2005, ICS '05.

[31]  John L. Henning SPEC CPU2006 benchmark descriptions , 2006, CARN.

[32]  Engin Ipek,et al.  Coordinated management of multiple interacting resources in chip multiprocessors: A machine learning approach , 2008, 2008 41st IEEE/ACM International Symposium on Microarchitecture.

[33]  Vanish Talwar,et al.  No "power" struggles: coordinated multi-level power management for the data center , 2008, ASPLOS.

[34]  Carla Schlatter Ellis,et al.  The Synergy Between Power-Aware Memory Systems and Processor Voltage Scaling , 2003, PACS.