A 6K-gate CMOS gate array

Combining advanced 2 /spl mu/m CMOS technology with a newly developed double layer metallization technology, a high-performance 6K-gate CMOS gate array has been developed, featuring an inverter propagation delay time of 0.4 ns with a power dissipation of 10 /spl mu/W/MHz/stage. As a demonstration vehicle of the high-performance gate array, a 16 bit/spl times/16 bit parallel multiplier has been designed and fabricated in which 3365 basic cells are used. Typical multiplying time has been measured to be 130 ns at a 5 MHz clock rate with a power dissipation of 275 mW.