Security algorithm circuit and data encryption method

The RC4 algorithm according to the present invention relates to a security algorithm circuits and data encryption method implemented in hardware. Secure algorithm circuit according to the present invention include the S box, read control logic, registers, and write control logic. The S boxes are the first and has a second port, in response to a clock signal and outputting the data via the first port, and at the same time receives the data through the second port. The read control logic is coupled to the first port, and controls the reading operation of the S box. The register stores the data output from the S box address and the output from the read control logic. The write control logic receives the address and data stored in the register, and controls the write operation of the S box. Secure algorithm circuit according to the invention is easy to design a secure algorithm because it separately provided with a write control logic and read control logic and by using the dual-port S-RAM because it operates in a pipelined manner to reduce the number of the clock compared with the conventional can.