On-chip cores take on yield problems

Yield and reliability have become critical issues for today's deep-submicron semiconductor technologies. Shrinking geometries have caused new effects, such as defects between the metal layers in an integrated circuit (IC), that increase the overall level of defect susceptibility. As a result, finer and denser fabrication can result in lower manufacturing yields, which in turn lengthen the production ramp-up period and the time it takes to get to volume manufacturing. In terms of reliability, transient and soft errors become more prevalent with fine-geometry, high-performance ICs. We need to be careful about such transients because they can cause failures in the field. There is a wide range of infrastructure IP (specialised onchip cores) appearing to address these challenges that will need to be used at key points in the silicon realisation flow. Some will be used in the design phase, some in manufacturing, and others in the field.