Discrete Vt assignment and gate sizing using a self-snapping continuous formulation
暂无分享,去创建一个
David Blaauw | Dennis Sylvester | Dushyant Sharma | Ashish Srivastava | Vladimir Zolotov | Saumil Shah
[1] David G. Chinnery,et al. Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization , 2003, ISLPED '03.
[2] Keshab K. Parhi,et al. Low power synthesis of dual threshold voltage CMOS VLSI circuits , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).
[3] H. B. Bakoglu,et al. Circuits, interconnections, and packaging for VLSI , 1990 .
[4] David Blaauw,et al. Achieving continuous VT performance in a dual VT process , 2005, ASP-DAC '05.
[5] Sachin S. Sapatnekar,et al. Convex delay models for transistor sizing , 2000, DAC.
[6] Dennis Sylvester,et al. A new threshold voltage assignment scheme for runtime leakage reduction in on-chip repeaters , 2004, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..
[7] Hanif D. Sherali,et al. Linear Programming and Network Flows , 1977 .
[8] Charlie Chung-Ping Chen,et al. Fast and effective gate-sizing with multiple-V/sub t/ assignment using generalized Lagrangian relaxation , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..
[9] James Tschanz,et al. Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors , 2002, DAC '02.
[10] A. Chatterjee,et al. Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits , 2001, IEEE Trans. Very Large Scale Integr. Syst..
[11] Martin D. F. Wong,et al. Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).
[12] David Blaauw,et al. Tutorial 2: Leakage Issues in IC Design: Trends, Estimation, and Avoidance , 2003, ICCAD 2003.
[13] Rajendran Panda,et al. Duet: an accurate leakage estimation and optimization tool for dual-Vt circuits , 2002, IEEE Trans. Very Large Scale Integr. Syst..
[14] Ankur Srivastava. Simultaneous Vt selection and assignment for leakage optimization , 2003, ISLPED '03.
[15] Brian W. Kernighan,et al. AMPL: A Modeling Language for Mathematical Programming , 1993 .
[16] Charlie Chung-Ping Chen,et al. Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian Relaxation , 2005, ASP-DAC.
[17] Mark C. Johnson,et al. Design and optimization of low voltage high performance dual threshold CMOS circuits , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).
[18] F. Brglez,et al. A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN , 1985 .