Germanium Multiple-Gate Field-Effect Transistors Formed on Germanium-on-Insulator Substrate

We demonstrate the integration of high performance p-channel Germanium Multiple-Gate Field-Effect Transistors (MuGFETs) on a Germanium-on-Insulator substrate. Detailed process conditions are documented in this paper. The effects of Ge fin doping concentration on the electrical performance of Ge MuGFETs are discussed, and this could be useful for further device optimization. It is found that a higher fin doping leads to better control of short-channel efforts of Ge MuGFETs but degrades the on-state current and transconductance. High on-state current for Ge MuGFETs is reported in this paper.

[1]  T. Lee,et al.  Demonstration of scaled Ge p-channel FinFETs integrated on Si , 2012, 2012 International Electron Devices Meeting.

[2]  Bin Liu,et al.  High-Performance Germanium $\Omega$ -Gate MuGFET With Schottky-Barrier Nickel Germanide Source/Drain and Low-Temperature Disilane-Passivated Gate Stack , 2012, IEEE Electron Device Letters.

[3]  A. Ogura,et al.  High-mobility and low-parasitic resistance characteristics in strained Ge nanowire pMOSFETs with metal source/drain structure formed by doping-free processes , 2012, 2012 Symposium on VLSI Technology (VLSIT).

[4]  C. Auth,et al.  A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors , 2012, 2012 Symposium on VLSI Technology (VLSIT).

[5]  N. Taoka,et al.  High mobility Ge pMOSFETs with 0.7 nm ultrathin EOT using HfO2/Al2O3/GeOx/Ge gate stacks fabricated by plasma post oxidation , 2012, 2012 Symposium on VLSI Technology (VLSIT).

[6]  P. Oldiges,et al.  Channel doping impact on FinFETs for 22nm and beyond , 2012, 2012 Symposium on VLSI Technology (VLSIT).

[7]  K. J. Kuhn,et al.  Considerations for Ultimate CMOS Scaling , 2012, IEEE Transactions on Electron Devices.

[8]  A. Hikavyy,et al.  Advancing CMOS beyond the Si roadmap with Ge and III/V devices , 2011, 2011 International Electron Devices Meeting.

[9]  C. Hu,et al.  Nearly defect-free Ge gate-all-around FETs on Si substrates , 2011, 2011 International Electron Devices Meeting.

[10]  R. Pillarisetty,et al.  Academic and industry research progress in germanium nanodevices , 2011, Nature.

[11]  G. Dewey,et al.  High mobility strained germanium quantum well field effect transistor as the p-channel device option for low power (Vcc = 0.5 V) III–V CMOS architecture , 2010, 2010 International Electron Devices Meeting.

[12]  L. Gomez,et al.  Enhanced Hole Mobility in High Ge Content Asymmetrically Strained-SiGe p-MOSFETs , 2010, IEEE Electron Device Letters.

[13]  N. Singh,et al.  CMOS compatible Ge/Si core/shell nanowire gate-all-around pMOSFET integrated with HfO2/TaN gate stack , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[14]  Emmanuel Augendre,et al.  Improved GeOI substrates for pMOSFET off-state leakage control , 2009 .

[15]  M. Vinet,et al.  Sub-100nm high-K metal gate GeOI pMOSFETs performance: Impact of the Ge channel orientation and of the source injection velocity , 2009, 2009 International Symposium on VLSI Technology, Systems, and Applications.

[16]  A. Dimoulas,et al.  Modeling of negatively charged states at the Ge surface and interfaces , 2009 .

[17]  S. Mantl,et al.  Schottky-barrier height tuning of Ni and Pt germanide/n-Ge contacts using dopant segregation , 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.

[18]  Vita Pi-Ho Hu,et al.  Investigation of electrostatic integrity for ultra-thin-body GeOI MOSFET using analytical solution of Poisson's equation , 2008, 2008 IEEE International Conference on Electron Devices and Solid-State Circuits.

[19]  Y. Nishi,et al.  High-Performance Gate-All-Around GeOI p-MOSFETs Fabricated by Rapid Melt Growth Using Plasma Nitridation and ALD $\hbox{Al}_{2}\hbox{O}_{3}$ Gate Dielectric and Self-Aligned NiGe Contacts , 2008, IEEE Electron Device Letters.

[20]  Geert Hellings,et al.  Germanium MOSFET Devices: Advances in Materials Understanding, Process Development, and Electrical Performance , 2008 .

[21]  John J. Hench,et al.  Forward solve algorithms for optical critical dimension metrology , 2008, SPIE Advanced Lithography.

[22]  Marc Meuris,et al.  Observation and Suppression of Nickel Germanide Overgrowth on Germanium Substrates with Patterned SiO2 Structures , 2008 .

[23]  K. Endo,et al.  Experimental Evaluation of Effects of Channel Doping on Characteristics of FinFETs , 2007, IEEE Electron Device Letters.

[24]  Raymond Woo,et al.  P-Channel Germanium FinFET Based on Rapid Melt Growth , 2007, IEEE Electron Device Letters.

[25]  H. B. Yao,et al.  Schottky barrier height in germanide/Ge contacts and its engineering through germanidation induced dopant segregation , 2007, 2007 International Workshop on Junction Technology.

[26]  Krishna C. Saraswat,et al.  High performance germanium MOSFETs , 2006 .

[27]  H. Dai,et al.  Parallel core-shell metal-dielectric-semiconductor germanium nanowires for high-current surround-gate field-effect transistors. , 2006, Nano letters.

[28]  Paul Zimmerman,et al.  Thin epitaxial si films as a passivation method for Ge(100) : Influence of deposition temperature on ge surface segregation and the high-k/Ge interface quality , 2006 .

[29]  Frederic Allibert,et al.  Germanium-on-insulator (GeOI) substrates—A novel engineered substrate for future high performance devices , 2006 .

[30]  Charles M. Lieber,et al.  Ge/Si nanowire heterostructures as high-performance field-effect transistors , 2006, Nature.

[31]  Krishna C. Saraswat,et al.  Germanium n-type shallow junction activation dependences , 2005 .

[32]  N. Lee,et al.  Dry Etching of TaN/HfO2 Gate Stack Structure by Cl2/SF6/Ar Inductively Coupled Plasma , 2005 .

[33]  M. Lundstrom On the mobility versus drain current relation for a nanoscale MOSFET , 2001, IEEE Electron Device Letters.

[34]  D. Antoniadis,et al.  On experimental determination of carrier velocity in deeply scaled NMOS: how close to the thermal limit? , 2001, IEEE Electron Device Letters.

[35]  Chenming Hu,et al.  Sub 50-nm FinFET: PMOS , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[36]  W. McGahan,et al.  Spectroscopic Ellipsometry and Reflectometry: A User's Guide , 1999 .

[37]  Mark S. Lundstrom Elementary scattering theory of the Si MOSFET , 1997, IEEE Electron Device Letters.

[38]  Sorin Cristoloveanu,et al.  Submicron SOI-MOSFETs for high temperature operation (300–600K) , 1997 .

[39]  A. Toriumi,et al.  Experimental study of threshold voltage fluctuation due to statistical variation of channel dopant number in MOSFET's , 1994 .

[40]  P. Karulkar Ultra-thin SOI MOSFETs at high temperature , 1993, Proceedings of 1993 IEEE International SOI Conference.

[41]  R. Loo,et al.  Short-channel epitaxial germanium PMOS transistors , 2010 .

[42]  R. Loo,et al.  Record ION/IOFF performance for 65nm Ge pMOSFET and novel Si passivation scheme for improved EOT scalability , 2008, 2008 IEEE International Electron Devices Meeting.

[43]  C. Hu,et al.  FinFET-a self-aligned double-gate MOSFET scalable to 20 nm , 2000 .