Lithography pattern line-edge roughness (LER) has important device implications such as device variability, current leakage and dielectric breakdown. This study characterizes how LER impacts device performance in terms of spatial frequency distribution. In the front-end of device fabrication, it is shown that low-frequency fin LER causes large FinFET device variability and becomes more severe for advanced device nodes. The effect of the dielectric/metal line LER spatial frequency distribution on the dielectric breakdown and resistance-capacitance (RC) variation for interconnects was studied. It is found that low-frequency LER introduces the highest electrostatic field due to surface charge localization, resulting in an increase in the occurrence of a dielectric breakdown path. The critical frequency range that contributes the most to device variability also evolves with device nodes. On the other hand, RC variation shows negligible dependency on LER amplitude and frequency.