论文信息 - Implementation of neural networks as CMOS integrated circuits

Implementation of neural networks as CMOS integrated circuits

A bit serial VLSI neural network is described from an initial architecture for a synapse array through to silicon layout and board design. The issues surrounding bit serial computation, and analog/digital arithmetic are discussed and the parallel development of a hybrid analog/digital neural network is outlined. Learning and recall capabilities are reported for the bit serial network along with a projected specification for a 64 neuron, bit serial board operating at 20 MHz. This technique is extended to a 256 (2562 synapses) network with an update time of 3ms, using a "paging" technique to time multiplex calculations through the synapse array.

Anthony V. W. Smith | Anthony V. W. Smith

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