A low power W-band PLL with 17-mW in 65-nm CMOS technology

This paper presents the design and experimental verification of a W-band phase-locked loop (PLL) realized in 65-nm digital CMOS process. The PLL incorporates the proposed divide-by-three frequency divider to relax the power/speed requirement for the succeeding divider chain. A distributed-LC tank is employed in the VCO as well, improving the tank quality factor and the circuit speed. Thus, the power is reduced significantly by the two circuit techniques mentioned above. The PLL can be locked from 78.2 to 79.0-GHz and dissipates 17-mW only from 1.0/0.8-V supplies excluding output buffers. The phase noise at 1-MHz and 10-MHz offset from the carrier are −78.9 and −109.1 dBc/Hz, respectively. The core area is 0.48 × 0.42 mm2.

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