Testing for faults, looking for defects

A commonly used criterion for evaluating tests for a VLSI chip is the coverage of modeled stuck-at faults. This coverage is deterministic, is easy to measure and has become an established standard. However, an often-asked question is: can the fault coverage tell us the defect level? Or, do we know how many defective chips will escape testing? This talk explains how thirty years of research provides some answers. An analysis of the test data for a Sematech chip gives a defect level of 1, 000 defective parts per million (DPM) for 99% fault coverage. It further calculates the fault coverage requirement as 99.9% to lower the defect level to 100 DPM. For today's large chips and system-on-chip (SOC) devices tests with such high coverage, if at all possible, are expensive to derive and expensive to apply. So, we pose a second question: how good are the stuck-fault coverage tests at detecting the presence of “real” defects, such as, to name a few, bridges, opens, shorts, or delays? Further analysis of the Sematech test data indicates that the stuck-at fault coverage may be a pessimistic indicator of the defect coverage. In other words, in trying to blindly increase the stuck-at fault coverage we may be chasing wrong targets. We summarize with thoughts on directions the industry is taking.