INSTRUCTION LEVEL PARALLELISM - THE ROLE OF ARCHITECTURE AND COMPILER

The instruction level parallelism (ILP) is not a new idea. It has been in practice since 1970 and became a much more significant force in computer design by 1980s. The researchers are continuously working on how to exploit ILP using aggressive techniques. To exploit ILP the role of compiler and Computer Architecture is very important. The compiler identifies the parallelism in the program and communicates it to the hardware (through dependences between operations). Compiler may re-order instructions to facilitate the task of hardware to extract the parallelism. The hardware determines at run-time when each operation is independent from others and perform scheduling, and there is no scanning of the sequential program to determine dependences. To achieve the high degree of ILP, it is necessary to execute the instruction at earliest possible time. The execution of instruction at earliest possible time is subject to availability of input operands and functional units. The compiler may additionally specify on which functional unit and in which cycle, an operation is executed. In this paper we present role of hardware and compiler to exploit instruction level parallelism.