Design and development of the first single-chip full-duplex OC48 traffic manager and ATM SAR SoC
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U. Joshi | Min Li | F. Chiu | A. Tsou | Xia Zhong | A. Ghosh | Ali Raza | A. Khan | K. B. Patel | A. Aurora | B. Parruck | A. Bagchi | B. Litinsky | E. Hong | E. Zhao | J. Ngo | K. Ko | L. Singh | P. Arnaudov | P. Wu | R. Ramakrishnan | R. Zecharia | S. Channabasappa | S. Kumar | S. Wattal | T. Wang | Z. Golan | Zunning Luo | D. Le | I. Ahmed | K. Y. Chow | H. Furuzono | D. Ge | M. Mueller | S. Nguyen | T. Nguyen | J. Saito | J. Shen | A. Todesco | D. Wang | S. Yang | J. Yu
[1] S. Nassif,et al. Delay variability: sources, impacts and trends , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).
[2] R. Mcpherson,et al. 260 Mb/s mixed-signal single-chip integrated system electronics for magnetic hard disk drives , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).
[3] Min Li,et al. A 150 MHz graphics rendering processor with 256 Mb embedded DRAM , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).
[4] Tadashi Matsumoto,et al. 9.6 A 150MHz Graphics Rendering Processor with 256Mb Embedded DRAM , 2001 .