S3CBench: Synthesizable Security SystemC Benchmarks for High-Level Synthesis

This work presents an open-source benchmark suite of synthesizable behavioral descriptions with different types of hardware Trojan. A repository of RT-level benchmarks with different types of Hardware Trojan is available at the Trust-hub (https://www.trust-hub.org/resources/benchmarks). Unfortunately, this benchmark suite misses completely the behavioral abstraction level. This work aims at bridging this gap by providing the first behavioral synthesis benchmark suite in a common language supported by all major HLS vendors (SystemC) which cover most of the hardware Trojan types. The designs have been created in such a way that the hardware Trojan cannot be found using standard software profiling techniques (i.e., 100% code coverage in most of the cases). This work also presents the obfuscated version of the benchmarks which makes it even hard to detect the hardware Trojans using the traditional verification approaches.

[1]  Masayoshi Yoshimura,et al.  A smart Trojan circuit and smart attack method in AES encryption circuits , 2013, 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS).

[2]  Mark Mohammad Tehranipoor,et al.  Hardware Trojan Detection and Isolation Using Current Integration and Localized Current Analysis , 2008, 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems.

[3]  Glenford J. Myers,et al.  Art of Software Testing , 1979 .

[4]  Michael S. Hsiao,et al.  Trusted RTL: Trojan detection methodology in pre-silicon designs , 2010, 2010 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST).

[5]  Philippe Coussy,et al.  High-Level Synthesis: from Algorithm to Digital Circuit , 2008 .

[6]  Simha Sethumadhavan,et al.  FANCI: identification of stealthy malicious logic using boolean functional analysis , 2013, CCS.

[7]  Christof Paar,et al.  A Design Methodology for Stealthy Parametric Trojans and Its Application to Bug Attacks , 2016, CHES.

[8]  Christos A. Papachristou,et al.  MERO: A Statistical Approach for Hardware Trojan Detection , 2009, CHES.

[9]  John D. Musa,et al.  Software-reliability-engineered testing practice (tutorial) , 1997, ICSE '97.

[10]  Mark Mohammad Tehranipoor,et al.  Benchmarking of Hardware Trojans and Maliciously Affected Circuits , 2017, Journal of Hardware and Systems Security.

[11]  Farinaz Koushanfar,et al.  A Survey of Hardware Trojan Taxonomy and Detection , 2010, IEEE Design & Test of Computers.

[12]  Mark Mohammad Tehranipoor,et al.  Trustworthy Hardware: Identifying and Classifying Hardware Trojans , 2010, Computer.

[13]  Mark Mohammad Tehranipoor,et al.  Protection Against Hardware Trojan Attacks: Towards a Comprehensive Solution , 2013, IEEE Design & Test.

[14]  Simeon C. Ntafos,et al.  An Evaluation of Random Testing , 1984, IEEE Transactions on Software Engineering.

[15]  Mark Mohammad Tehranipoor,et al.  A Clock Sweeping Technique for Detecting Hardware Trojans Impacting Circuits Delay , 2013, IEEE Design & Test.

[16]  Michael S. Hsiao,et al.  A Novel Sustained Vector Technique for the Detection of Hardware Trojans , 2009, 2009 22nd International Conference on VLSI Design.

[17]  Kaushik Roy,et al.  Multiple-parameter side-channel analysis: A non-invasive hardware Trojan detection approach , 2010, 2010 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST).

[18]  Benjamin Carrión Schäfer,et al.  S2CBench: Synthesizable SystemC Benchmark Suite for High-Level Synthesis , 2014, IEEE Embedded Systems Letters.

[19]  Farinaz Koushanfar,et al.  High-sensitivity hardware Trojan detection using multimodal characterization , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).