ESD protection design for mixed-voltage I/O buffer with substrate-triggered circuit

A substrate-triggered technique is proposed to improve the electrostatic discharge (ESD) robustness of a stacked-nMOS device in the mixed-voltage I/O circuit. The substrate-triggered technique can further lower the trigger voltage of a stacked-nMOS device to ensure effective ESD protection for mixed-voltage I/O circuits. The proposed ESD protection circuit with substrate-triggered design for a 2.5-V/3.3-V-tolerant mixed-voltage I/O circuit has been fabricated and verified in a 0.25-/spl mu/m salicided CMOS process. The substrate-triggered circuit for a mixed-voltage I/O buffer to meet the desired circuit application in different CMOS processes can be easily adjusted by using HSPICE simulation. Experimental results have confirmed that the human- body-model (HBM) ESD robustness of a mixed-voltage I/O circuit can be increased /spl sim/60% by this substrate-triggered design.

[1]  J.W. Miller,et al.  Engineering the cascoded NMOS output buffer for maximum V/sub t1/ , 2000, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476).

[2]  K.-H. Lin,et al.  On-chip ESD protection design with substrate-triggered technique for mixed-Voltage I/O circuits in subquarter-micrometer CMOS Process , 2004, IEEE Transactions on Electron Devices.

[3]  C. Lage,et al.  A versatile 0.25 micron CMOS technology , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[4]  Steven H. Voldman,et al.  ESD protection in a mixed-voltage interface and multirail disconnected power grid environment in 0.50- and 0.25-/spl mu/m channel length CMOS technologies , 1995 .

[5]  J. McVittie,et al.  Thin-oxide damage from gate charging during plasma processing , 1992, IEEE Electron Device Letters.

[6]  E. C. Dijkmans,et al.  A 3/5 V compatible I/O buffer , 1995 .

[7]  G. P. Singh,et al.  High-voltage-tolerant I/O buffers with low-voltage CMOS process , 1999, IEEE J. Solid State Circuits.

[8]  Timothy J. Maloney,et al.  Basic ESD and I/O Design , 1998 .

[9]  Edward J. Nowak,et al.  High-performance sub-0.08 /spl mu/m CMOS with dual gate oxide and 9.7 ps inverter delay , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[10]  C. Duvvury,et al.  Substrate pump NMOS for ESD protection applications , 2000, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476).

[11]  C. Hu,et al.  Thin oxide damage by plasma etching and ashing processes , 1992, 30th Annual Proceedings Reliability Physics 1992.

[12]  Tung-Yang Chen,et al.  Investigation of the gate-driven effect and substrate-triggered effect on ESD robustness of CMOS devices , 2001 .

[13]  E. Rosenbaum,et al.  Substrate resistance modeling and circuit-level simulation of parasitic device coupling effects for CMOS I/O circuits under ESD stress , 1998, Electrical Overstress/ Electrostatic Discharge Symposium Proceedings. 1998 (Cat. No.98TH8347).

[14]  W. Fichtner,et al.  TCAD software for ESD on-chip protection design , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[15]  Ming-Dou Ker,et al.  ESD protection design for mixed-voltage-tolerant I/O buffers with substrate-triggered technique , 2003, IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings..

[16]  Connor,et al.  Dynamic Dielectric Protection For I/0 Circuits Fabricated In A 2.5V CMOS Technology Interfacing To A 3.3V LVTTL Bus , 1997, Symposium 1997 on VLSI Circuits.

[17]  Charvaka Duvvury,et al.  Substrate triggering and salicide effects on ESD performance and protection circuit design in deep submicron CMOS processes , 1995, Proceedings of International Electron Devices Meeting.

[18]  H. Sanchez,et al.  A versatile 3.3 V/2.5 V/1.8 V CMOS I/O driver built in a 0.2 /spl mu/m 3.5 nm Tox 1.8 V CMOS technology , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[19]  Anne-Johan Annema,et al.  5.5-V I/O in a 2.5-V 0.25-/spl mu/m CMOS technology , 2001 .

[20]  Takayasu Sakurai,et al.  3.3V-5V compatible I/O circuit without thick gate oxide , 1992, 1992 Proceedings of the IEEE Custom Integrated Circuits Conference.

[21]  M. Ker.  Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI , 1999 .

[22]  Ming-Dou Ker,et al.  ESD protection design for mixed-voltage I/O circuit with substrate-triggered technique in sub-quarter-micron CMOS process , 2002, Proceedings International Symposium on Quality Electronic Design.

[23]  D. B. Krakauer,et al.  ESD protection for mixed-voltage I/O using NMOS transistors stacked in a cascode configuration , 1998 .

[24]  S. Mittl,et al.  Accelerated gate-oxide breakdown in mixed-voltage I/O circuits , 1997, 1997 IEEE International Reliability Physics Symposium Proceedings. 35th Annual.

[25]  Charvaka Duvvury,et al.  Electrothermal simulation of electrical overstress in advanced nMOS ESD I/O protection devices , 1993, Proceedings of IEEE International Electron Devices Meeting.