Response-Time Analysis for Task Chains with Complex Precedence and Blocking Relations

For the development of complex software systems, we often resort to component-based approaches that separate the different concerns, enhance verifiability and reusability, and for which microkernel-based implementations are a good fit to enforce these concepts. Composing such a system of several interacting software components will, however, lead to complex precedence and blocking relations, which must be taken into account when performing latency analysis. When modelling these systems by classical task graphs, some of these effects are obfuscated and tend to render such an analysis either overly pessimistic or even optimistic. We therefore firstly present a novel task (meta-)model that is more expressive and accurate w.r.t. these (functional) precedence and mutual blocking relations. Secondly, we apply the busy-window approach and formulate a modular response-time analysis on task-chain level suitable but not restricted to static-priority scheduled systems. We show that the conjunction of both concepts allows the calculation of reasonably tight latency bounds for scenarios not adequately covered by related work.

[1]  Rolf Ernst,et al.  Exploiting inter-event stream correlations between output event streams of non-preemptively scheduled tasks , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[2]  Rolf Ernst,et al.  Providing accurate event models for the analysis of heterogeneous multiprocessor systems , 2008, CODES+ISSS '08.

[3]  Rolf Ernst,et al.  Response-Time Analysis for Task Chains in Communicating Threads , 2016, 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS).

[4]  Rolf Ernst,et al.  A recursive approach to end-to-end path latency computation in heterogeneous multiprocessor systems , 2009, CODES+ISSS '09.

[5]  Rolf Ernst,et al.  System-level timing feasibility test for cyber-physical automotive systems , 2016, 2016 11th IEEE Symposium on Industrial Embedded Systems (SIES).

[6]  Lothar Thiele,et al.  Modeling structured event streams in system level performance analysis , 2010, LCTES '10.

[7]  Alexander Wieder,et al.  A Blocking Bound for Nested FIFO Spin Locks , 2016, 2016 IEEE Real-Time Systems Symposium (RTSS).

[8]  Marco Bekooij,et al.  Combining Offsets with Precedence Constraints to Improve Temporal Analysis of Cyclic Real-Time Streaming Applications , 2016, 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS).

[9]  Alexander Böttcher,et al.  Timeslice Donation in Component-Based Systems , 2010 .

[10]  Gabriel Parmer The Case for Thread Migration : Predictable IPC in a Customizable and Reliable OS , 2010 .

[11]  John P. Lehoczky,et al.  Timing Analysis for Fixed-Priority Scheduling of Hard Real-Time Systems , 1994, IEEE Trans. Software Eng..

[12]  Lui Sha,et al.  Priority Inheritance Protocols: An Approach to Real-Time Synchronization , 1990, IEEE Trans. Computers.

[13]  Jochen Liedtke,et al.  Improving IPC by kernel design , 1994, SOSP '93.

[14]  Frank Slomka,et al.  Reducing Response Times by Competition Based Dependencies , 2011, MBMV.

[15]  Jukka Mäki-Turja,et al.  Efficient implementation of tight response-times for tasks with offsets , 2008, Real-Time Systems.

[16]  Michael González Harbour,et al.  Exploiting precedence relations in the schedulability analysis of distributed real-time systems , 1999, Proceedings 20th IEEE Real-Time Systems Symposium (Cat. No.99CB37054).

[17]  Rolf Ernst,et al.  Response-time analysis for non-preemptive scheduling in multi-core systems with shared resources , 2012, 7th IEEE International Symposium on Industrial Embedded Systems (SIES'12).

[18]  Rolf Ernst,et al.  Bounding deadline misses in weakly-hard real-time systems with task dependencies , 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

[19]  Gernot Heiser,et al.  From L3 to seL4 what have we learnt in 20 years of L4 microkernels? , 2013, SOSP.

[20]  Martin Stigge Real-Time Workload Models : Expressiveness vs. Analysis Efficiency , 2014 .

[21]  Rolf Ernst,et al.  Improved offset-analysis using multiple timing-references , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[22]  Bran Selic,et al.  Modeling and Analysis of Real-Time and Embedded Systems with UML and MARTE: Developing Cyber-Physical Systems , 2013 .

[23]  Marco Panunzio,et al.  Integrating Formal Timing Analysis in the Real-Time Software Development Process , 2015, WOSP '15.

[24]  Dhiraj K. Pradhan,et al.  Design Automation and Test in Europe (DATE) , 2014 .