Invited: Software Defined Accelerators From Learning Tools Environment
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Joseph Manzano | Marco Minutoli | Vito Giovanni Castellana | Antonino Tumeo | David Brooks | Gu-Yeon Wei | Vinay Amatya | Vinay C. Amatya | Gu-Yeon Wei | D. Brooks | Antonino Tumeo | Marco Minutoli | J. Manzano
[1] Xuehai Zhou,et al. PuDianNao: A Polyvalent Machine Learning Accelerator , 2015, ASPLOS.
[2] Trevor Darrell,et al. Caffe: Convolutional Architecture for Fast Feature Embedding , 2014, ACM Multimedia.
[3] Antonino Tumeo,et al. Mapping and scheduling of parallel C applications with Ant Colony Optimization onto heterogeneous reconfigurable MPSoCs , 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).
[4] Bertrand A. Maher,et al. Glow: Graph Lowering Compiler Techniques for Neural Networks , 2018, ArXiv.
[5] Marco Minutoli,et al. Efficient synthesis of graph methods: A dynamically scheduled architecture , 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
[6] Hadi Esmaeilzadeh,et al. TABLA: A unified template-based framework for accelerating statistical machine learning , 2016, 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA).
[7] Jim D. Garside,et al. SpiNNaker: Design and Implementation of a GALS Multicore System-on-Chip , 2011, JETC.
[8] Asit K. Mishra,et al. From high-level deep neural models to FPGAs , 2016, 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).
[9] Gianluca Palermo,et al. Improving evolutionary exploration to area-time optimization of FPGA designs , 2008, J. Syst. Archit..
[10] Pier Luca Lanzi,et al. Ant Colony Heuristic for Mapping and Scheduling Tasks and Communications on Heterogeneous Embedded Systems , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[11] Gianluca Palermo,et al. An Evolutionary Approach to Area-Time Optimization of FPGA designs , 2007, 2007 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation.
[12] Vito Giovanni Castellana,et al. An adaptive Memory Interface Controller for improving bandwidth utilization of hybrid and reconfigurable systems , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[13] Haichen Shen,et al. TVM: An Automated End-to-End Optimizing Compiler for Deep Learning , 2018 .
[14] Joel Emer,et al. Eyeriss: a spatial architecture for energy-efficient dataflow for convolutional neural networks , 2016, CARN.
[15] Pier Luca Lanzi,et al. Mapping pipelined applications onto heterogeneous embedded systems: a bayesian optimization algorithm based approach , 2009, CODES+ISSS '09.
[16] Uday Bondhugula,et al. MLIR: A Compiler Infrastructure for the End of Moore's Law , 2020, ArXiv.
[17] Frédo Durand,et al. Halide , 2017, Commun. ACM.
[18] Pier Luca Lanzi,et al. Multiprocessor systems-on-chip synthesis using multi-objective evolutionary computation , 2010, GECCO '10.