Thermal effects of leakage power in 3D ICs

Thermal issue is a primary concern in three-dimensional (3D) integrated circuit (IC) design. In modern IC design, leakage power is becoming a key design challenge which contributes to thermal issues. Due to technology scaling, the leakage power is rising so quickly that it largely increases the die temperature. In this paper, we first investigate the impact of leakage power on thermal profile in 3D packings, and then we analyze thermal and leakage aware floorplanning based on 3D-STAF[17] platform. Finally, the effects of thermal controls including the thermal-aware floorplanner and thermal via insertion for thermal management are analyzed in experiment results. The results show that leakage power increases the maximal temperature on the chip greatly about50%. Hence, the required thermal via number also increases greatly about 52.6%.

[1]  A. Eltawil,et al.  Managing leakage power and reliability in hot chips using system floorplanning and SRAM design , 2008, 2008 14th International Workshop on Thermal Inveatigation of ICs and Systems.

[2]  Yusuf Leblebici,et al.  Through Silicon Via-Based Grid for Thermal Control in 3D Chips , 2009, NanoNet.

[3]  Kevin Skadron,et al.  A Case for Thermal-Aware Floorplanning at the Microarchitectural Level , 2005, J. Instr. Level Parallelism.

[4]  Fei Li,et al.  Microarchitecture level power and thermal simulation considering temperature dependent leakage model , 2003, ISLPED '03.

[5]  Li Shang,et al.  ISAC: Integrated Space-and-Time-Adaptive Chip-Package Thermal Analysis , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Jason Cong,et al.  Thermal-driven multilevel routing for 3-D ICs , 2005, Asia and South Pacific Design Automation Conference.

[7]  Nikil D. Dutt,et al.  STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs , 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

[8]  Nikil D. Dutt,et al.  Floorplan driven leakage power aware IP-based SoC design space exploration , 2006, Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06).

[9]  Frank M. Johannes,et al.  Generic global placement and floorplanning , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[10]  Qiang Zhou,et al.  3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[11]  Mircea R. Stan,et al.  System level leakage reduction considering the interdependence of temperature and leakage , 2004, Proceedings. 41st Design Automation Conference, 2004..

[12]  Sung Kyu Lim,et al.  Multi-functional interconnect co-optimization for fast and reliable 3D stacked ICs , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[13]  Bryan Black,et al.  3D processing technology and its impact on iA32 microprocessors , 2004, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

[14]  David Blaauw,et al.  Leakage power reduction using stress-enhanced layouts , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[15]  Nikil D. Dutt,et al.  LEAF: A System Level Leakage-Aware Floorplanner for SoCs , 2007, 2007 Asia and South Pacific Design Automation Conference.

[16]  S. Nassif,et al.  Full chip leakage-estimation considering power supply and temperature variations , 2003, Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03..

[17]  William J. Bowhill,et al.  Design of High-Performance Microprocessor Circuits , 2001 .

[18]  Jason Cong,et al.  A thermal-driven floorplanning algorithm for 3D ICs , 2004, ICCAD 2004.

[19]  Kevin Skadron,et al.  Microarchitectural Floorplanning for Thermal Management: A Technical Report , 2005 .

[20]  Kevin Skadron,et al.  The need for a full-chip and package thermal model for thermally optimized IC designs , 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

[21]  Qiang Zhou,et al.  Thermal Effects with Leakage Power Considered in 2D/3D Floorplanning , 2007, 2007 10th IEEE International Conference on Computer-Aided Design and Computer Graphics.