Runtime Verification: 19th International Conference, RV 2019, Porto, Portugal, October 8–11, 2019, Proceedings

The Monitoring and Checking (MaC) project gave rise to a framework for runtime monitoring with respect to formally specified properties, which later came to be known as runtime verification. The project also built a pioneering runtime verification tool, Java-MaC, that was an instantiation of the approach to check properties of Java programs. In this retrospective, we discuss decisions made in the design of the framework and summarize lessons learned in the course of the project.

[1]  Yutao Liu,et al.  CFIMon: Detecting violation of control flow integrity using performance counters , 2012, IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2012).

[2]  Krishnendu Chatterjee,et al.  Environment Assumptions for Synthesis , 2008, CONCUR.

[3]  Martin Leucker,et al.  Runtime Verification for LTL and TLTL , 2011, TSEM.

[4]  Andrew C. Myers,et al.  Language-based information-flow security , 2003, IEEE J. Sel. Areas Commun..

[5]  Zohar Manna,et al.  Temporal verification of reactive systems - safety , 1995 .

[6]  Tevfik Bultan,et al.  Profit: Detecting and Quantifying Side Channels in Networked Applications , 2019, NDSS.

[7]  Grigore Rosu,et al.  Rewriting-Based Techniques for Runtime Verification , 2005, Automated Software Engineering.

[8]  Li Tan,et al.  Model-based self-monitoring embedded programs with temporal logic specifications , 2005, ASE.

[9]  Chao Wang,et al.  Mitigating power side channels during compilation , 2019, ESEC/SIGSOFT FSE.

[10]  Edmund M. Clarke,et al.  Symbolic Model Checking: 10^20 States and Beyond , 1990, Inf. Comput..

[11]  Doron A. Peled,et al.  Monitoring Distributed Systems Using Knowledge , 2011, FMOODS/FORTE.

[12]  Marco Bozzano,et al.  Symbolic Synthesis of Observability Requirements for Diagnosability , 2012, AAAI.

[13]  Yliès Falcone,et al.  Decentralised LTL monitoring , 2016, Formal Methods Syst. Des..

[14]  Raja Sengupta,et al.  Diagnosability of discrete-event systems , 1995, IEEE Trans. Autom. Control..

[15]  Pavol Cerný,et al.  Data-Driven Debugging for Functional Side Channels , 2018, NDSS.

[16]  Xiao Liu,et al.  CacheD: Identifying Cache-Based Timing Channels in Production Software , 2017, USENIX Security Symposium.

[17]  Amir Pnueli,et al.  Algorithmic Verification of Linear Temporal Logic Specifications , 1998, ICALP.

[18]  Philippe Schnoebelen,et al.  Temporal logic with forgettable past , 2002, Proceedings 17th Annual IEEE Symposium on Logic in Computer Science.

[19]  Randal E. Bryant,et al.  Binary Decision Diagrams , 2018, Handbook of Model Checking.

[20]  Joseph Y. Halpern,et al.  The complexity of reasoning about knowledge and time , 1986, STOC '86.

[21]  Zohar Manna,et al.  The Temporal Logic of Reactive and Concurrent Systems , 1991, Springer New York.

[22]  Grigore Rosu,et al.  Synthesizing Monitors for Safety Properties , 2002, TACAS.

[23]  Bernd Finkbeiner,et al.  Does It Pay to Extend the Perimeter of a World Model? , 2011, FM.

[24]  Meng Wu,et al.  Eliminating timing side-channel leaks using program repair , 2018, ISSTA.

[25]  Pavol Cerný,et al.  Differential Performance Debugging with Discriminant Regression Trees , 2017, AAAI.

[26]  Dejan Nickovic,et al.  Runtime Monitoring with Recovery of the SENT Communication Protocol , 2017, CAV.

[27]  Martin Leucker,et al.  A brief account of runtime verification , 2009, J. Log. Algebraic Methods Program..

[28]  Insup Lee,et al.  Model-based testing and monitoring for hybrid embedded systems , 2004, Proceedings of the 2004 IEEE International Conference on Information Reuse and Integration, 2004. IRI 2004..

[29]  Ariel Fuxman,et al.  Formal analysis of early requirements specifications , 2001 .

[30]  Yang Liu,et al.  Trace-Length Independent Runtime Monitoring of Quantitative Policies in LTL , 2015, FM.

[31]  George S. Avrunin,et al.  Patterns in property specifications for finite-state verification , 1999, Proceedings of the 1999 International Conference on Software Engineering (IEEE Cat. No.99CB37002).

[32]  Chin-Laung Lei,et al.  Temporal Reasoning Under Generalized Fairness Constraints , 1986, STACS.

[33]  Jerry den Hartog,et al.  From System Specification to Anomaly Detection (and back) , 2017, CPS-SPC@CCS.

[34]  William Whittaker,et al.  Autonomous Driving in Traffic: Boss and the Urban Challenge , 2009, AI Mag..

[35]  Alessandro Cimatti,et al.  NuRV: A nuXmv Extension for Runtime Verification , 2019, RV.

[36]  Wilhelm Ackermann,et al.  Solvable Cases Of The Decision Problem , 1954 .

[37]  Martin Leucker,et al.  Sliding between Model Checking and Runtime Verification , 2012, RV.

[38]  Pavol Cerný,et al.  Discriminating Traces with Time , 2017, TACAS.

[39]  Alexander Aiken,et al.  Secure Information Flow as a Safety Problem , 2005, SAS.

[40]  Edmund M. Clarke,et al.  Another Look at LTL Model Checking , 1994, CAV.

[41]  Kenneth L. McMillan,et al.  Symbolic model checking , 1992 .

[42]  Geoffrey Smith,et al.  On the Foundations of Quantitative Information Flow , 2009, FoSSaCS.

[43]  Mounir Ghogho,et al.  Deep learning approach for Network Intrusion Detection in Software Defined Networking , 2016, 2016 International Conference on Wireless Networks and Mobile Communications (WINCOM).

[44]  Sahika Genc,et al.  Predictability in Discrete-Event Systems Under Partial Observation1 , 2007 .

[45]  Xian Zhang,et al.  Runtime Verification with Predictive Semantics , 2012, NASA Formal Methods.

[46]  Marco Roveri,et al.  The nuXmv Symbolic Model Checker , 2014, CAV.

[47]  Amir Pnueli,et al.  Synthesis of Reactive(1) Designs , 2006, VMCAI.

[48]  Martin Kardos,et al.  Model-based Runtime Verification Framework for Self-optimizing Systems , 2006, RV@CAV.

[49]  Pavol Cerný,et al.  Quantitative Mitigation of Timing Side Channels , 2019, CAV.

[50]  Gordon J. Pace,et al.  A Model-Based Approach to Combining Static and Dynamic Verification Techniques , 2016, ISoLA.

[51]  Klaus Havelund,et al.  A Tutorial on Runtime Verification , 2013, Engineering Dependable Software Systems.

[52]  Christian Colombo,et al.  Organising LTL Monitors over Distributed Systems with a Global Clock , 2014, RV.

[53]  Chao Wang,et al.  CANAL: A Cache Timing Analysis Framework via LLVM Transformation , 2018, 2018 33rd IEEE/ACM International Conference on Automated Software Engineering (ASE).

[54]  Yi Zhang,et al.  RV-Monitor: Efficient Parametric Runtime Verification with Simultaneous Properties , 2014, RV.

[55]  Stéphane Lafortune,et al.  Predictability of event occurrences in partially-observed discrete-event systems , 2009, Autom..