El proyecto realizado consiste en la implementacion de una herramienta capaz de simular el comportamiento descrito en una logica desarrollada (HOTL: Hypotheses and observations testing logic), en un excelente trabajo de investigacion, por parte de nuestro profesor director de proyecto D. Ismael Rodriguez Laguna y sus dos companeros D. Manuel Nunez y Dna. Mercedes G. Merayo.
La implementacion ha sido integrada en una interfaz grafica que nos permitira ejecutar una seria de reglas definidas en la logica dado un modelo, y dadas una especificacion concreta, unas observaciones y unas hipotesis y la aplicacion de las reglas sobre estos elementos, nos diga si la implementacion es conforme o no respecto de la especificacion. Todo esto mostrandose de manera grafica para que el usuario sea consciente de lo ocurrido en cada momento, como por ejemplo; la carga de la especificacion, de las observaciones e hipotesis, los modelos generados a partir de las observaciones, la generacion de modelos que implica la ejecucion de las reglas una a una, etc.
La herramienta ha sido implementada sobre una plataforma Java y su diseno se ha realizado llevando a cabo tecnicas y metodos empleados en ingenieria del software, tales como un arquitectura clara de la aplicacion (que facilitara la ampliacion futura de la herramienta), uso de patrones de diseno, division del trabajo en iteraciones, etc.,
ademas del uso de conocimientos de metodologia y tecnologia de la programacion para el desarrollo de ciertos algoritmos necesarios para la implementacion de la logica.[ABSTRACT]The made project consists of the implementation of a tool able to simulate the behavior described in a developed logic (HOTL: Hypotheses and observations testing
logic), in an excellent work of investigation, on the part of our professor director of project D. Ismael Rodriguez Laguna and their two companions D. Manuel Nunez and
Dna. Mercedes G. Merayo.[ABSTRACT]
The implementation has been integrated in a graphical interface that will allow us to execute serious of rules defined in the given logic a model, and given a concrete
specification, observations and a hypothesis and the application of the rules on these elements, says to us if the implementation is in agreement or nonrespect to the
specification. All this being of graphical way so that the user is conscious of the happened thing at every moment, like for example; the load of the specification, the
observations and hypothesis, the models generated from the observations, the generation of models that the execution of rules one to one implies, etc.
The tool has been implemented on a Java platform and its technical design has been made carrying out and used methods in engineering of the software, such as a
clear architecture of the application (that it will facilitate the future extension of the tool), use of design patterns, division of the work in iterations, etc., in addition to the use of knowledge of methodology and technology of the programming for the development of certain necessary algorithms for the implementation of the logic.
[1]
David Lee,et al.
Principles and methods of testing finite state machines-a survey
,
1996,
Proc. IEEE.
[2]
David Lee,et al.
A formal approach for passive testing of protocol data portions
,
2002,
10th IEEE International Conference on Network Protocols, 2002. Proceedings..
[3]
Ana R. Cavalli,et al.
Fast Testing of Critical Properties through Passive Testing
,
2003,
TestCom.
[4]
Mercedes G. Merayo,et al.
A Logic for Assessing Sets of Heterogeneous Testing Hypotheses
,
2006,
TestCom.
[5]
Alfred V. Aho,et al.
An optimization technique for protocol conformance test generation based on UIO sequences and rural Chinese postman tours
,
1991,
IEEE Trans. Commun..
[6]
M. Ümit Uyar,et al.
Finite State Machine Based Formal Methods in Protocol Conformance Testing: From Theory to Implementation
,
1991,
Comput. Networks ISDN Syst..
[7]
Deepinder P. Sidhu,et al.
Formal Methods for Protocol Testing: A Detailed Study
,
1989,
IEEE Trans. Software Eng..
[8]
Tsun S. Chow,et al.
Testing Software Design Modeled by Finite-State Machines
,
1978,
IEEE Transactions on Software Engineering.
[9]
G. Bochmann,et al.
Testing deterministic implementations from nondeterministic FSM specifications
,
1996
.
[10]
Ana Cavalli,et al.
A Pragmatic Approach to Generating Test Sequences for Embedded Systems
,
1997
.
[11]
Stephan Merz,et al.
Model Checking
,
2000
.
[12]
Ferhat Khendek,et al.
Test Selection Based on Finite State Models
,
1991,
IEEE Trans. Software Eng..
[13]
Ana R. Cavalli,et al.
A passive testing approach based on invariants: application to the WAP
,
2005,
Comput. Networks.
[14]
Manuel Núñez,et al.
Encoding PAMR into (Timed) EFSMs
,
2002,
FORTE.
[15]
Robert M. Hierons.
Comparing test sets and criteria in the presence of test hypotheses and fault domains
,
2002,
TSEM.
[16]
Jan Tretmans,et al.
Test Generation with Inputs, Outputs and Repetitive Quiescence
,
1996,
Softw. Concepts Tools.
[17]
Eleftherakis G,et al.
Towards Model Checking of Finite State Machines Extended with Memory through Refinement
,
2001
.
[18]
Simeon C. Ntafos,et al.
A Comparison of Some Structural Testing Strategies
,
1988,
IEEE Trans. Software Eng..
[19]
Mark Harman,et al.
Testing conformance of a deterministic implementation against a non-deterministic stream X-machine
,
2004,
Theor. Comput. Sci..
[20]
Alexandre Petrenko,et al.
Fault Model-Driven Test Derivation from Finite State Models: Annotated Bibliography
,
2000,
MOVEP.
[21]
Ana R. Cavalli,et al.
New approaches for passive testing using an Extended Finite State Machine specification
,
2003,
Inf. Softw. Technol..