A programmable pruning level control based MPEG video encoder

This paper proposes an efficient implementation of a Programmable Pruning Level Control (PPLC) based video encoder for real time image compression applications. The implementation is capable of processing good quality monochrome images of sizes up to 1200/spl times/1024 pixels and color images 1024/spl times/1024/spl times/768 pixels, both at the rate of 25 frames per second. The design fits into two pieces of a commercially available Embedded Programmable Logic Devices (EPLDs) and can be used directly as a coprocessor on a PC bus.

[2]  S. Ramachandran,et al.  Parallel implementation of 2D-discrete cosine transform using EPLDs , 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).

[3]  Chen-Mie Wu,et al.  A SIMD-systolic architecture and VLSI chip for the two-dimensional DCT and IDCT , 1993 .

[4]  S. Ramachandran,et al.  Design and implementation of an EPLD-based variable length coder for real time image compression applications , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[5]  V. K. Prasanna,et al.  Area efficient VLSI architectures for Huffman coding , 1993 .

[6]  S. Ramachandran,et al.  EPLD-based architecture of real time 2D-discrete cosine transform and quantization for image compression , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[7]  Liang-Gee Chen,et al.  A VLSI architecture design of VLC encoder for high data rate video/image coding , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).