A new design to prevent fault equivalence in PLAs

The fault equivalence problem in programmable logic arrays (PLAs) is introduced. Some design rules are proposed. Based on the pseudoexhaustive testable PLA structure, a diagnosis algorithm was developed and implemented on a SUN 3/110 workstation in C language. Experimental results show that this design and the algorithm are quite efficient for PLA fault diagnosis.<<ETX>>

[1]  Hideo Fujiwara,et al.  Implementing a Built-In Self-Test PLA Design , 1985, IEEE Design & Test of Computers.

[2]  K. S. Ramanatha,et al.  An On-Line Algorithm for the Location of Cross Point Faults in Programmable Logic Arrays , 1983, IEEE Transactions on Computers.

[3]  Sudhakar M. Reddy,et al.  On the Design of Random Pattern Testable PLAs , 1986, ITC.

[4]  Edward J. McCluskey.  Verification Testing - A Pseudoexhaustive Test Technique , 1984, IEEE Trans. Computers.

[5]  H. Fujiwara.  A design of programmable logic arrays with random pattern-testability , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  Sudhakar M. Reddy,et al.  On the Design of Pseudoexhaustive Testable PLA's , 1988, IEEE Trans. Computers.

[7]  Edward J. McCluskey,et al.  Lower Overhead Design for Testability of Programmable Logic Arrays , 1986, IEEE Transactions on Computers.

[8]  Norbert Wehn,et al.  A defect-tolerant and fully testable PLA , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..

[9]  W. Kent Fuchs,et al.  Fault Diagnosis and Spare Allocation for Yield Enhancement in Large Reconfigurable PLA's , 1992, IEEE Trans. Computers.