A 300 MHz 4-Mb wave-pipeline CMOS SRAM using a multi-phase PLL

This 4 Mb (64 k/spl times/64) synchronous wave-pipeline CMOS SRAM is fabricated by 0.25 /spl mu/m CMOS for cache memories. It achieves fully-random 300 MHz operation at a 2.5 V supply. The bandwidth is 2.4 GB/s; the highest value reported. This frequency is achieved through multi-phase active pulse control (MPAC), in which active pulse signals generated by a multi-phase PLL control the SRAM data path. The longest data path delay is shortened by dynamic decoders and current sense amplifiers.