Design of Reduced Instruction Set Computer Processor Based on Field Programmable Gate Array

This paper designs a embedded Reduced Instruction Set Computer(RISC) Central Processing Unit(CPU) based on Field Programmable Gate Array(FPGA) platform.The instruction set is designed refer to Microprocessor without Interlocked Pipeline Stage(MIPS) instruction set principle.By analyzing the process of each instruction,the 5-stage pipeline of embedded CPU is built.It adopts data forwarding technology and software compiler method to solve pipeline-related problem.The key modules of CPU: Arithmetic Logic Unit(ALU),control unit,instruction cache are designed.Verification results show that the embedded RISC CPU speed and stability meet the design requirements.