Probe test yield optimization based on canonical correlation analysis between process control monitoring variables and probe bin variables

Process control monitoring (PCM) data provide information that is used to track abnormal processes and estimate various probe bin yields. However, multi-dimensional information has not yet been fully utilized from both PCM data and probe bins. In this paper, we proposed a canonical correlation analysis in order to investigate the relationship between multiple PCM variables and various probe bin variables. Polynomial regression was also employed as a methodology for maximizing the performance yield based on the results of the canonical correlation analysis. Two conclusions were drawn from the results of this research. First, the PCM variables that affected the probe bins were contact resistance, sheet resistance, and Isat_P4H as well as threshold voltage (Vt) during the process tuning step. Second, the typical values of Vtl_P4H and Isat_P4H should be changed in order to maximize the performance yield. The proposed method can be used for yield improvement and as a problem-solving approach for optimizing the IC process.

[1]  S. Smith,et al.  Extraction of Sheet Resistance and Line Width From All-Copper ECD Test Structures Fabricated From Silicon Preforms , 2008, IEEE Transactions on Semiconductor Manufacturing.

[2]  Chen-Fu Chien,et al.  Hybrid data mining approach for pattern extraction from wafer bin map to improve yield in semiconductor manufacturing , 2007, International Journal of Production Economics.

[3]  K. Agarwal,et al.  Fast Characterization of Threshold Voltage Fluctuation in MOS Devices , 2008, IEEE Transactions on Semiconductor Manufacturing.

[4]  Shu-Kai S. Fan.  Multiple-input single-output (MISO) ridge-optimizing quality controller for semiconductor manufacturing processes , 2005 .

[5]  D. Look,et al.  Mobility measurements with a standard contact resistance pattern , 1987, IEEE Electron Device Letters.

[6]  Chen-Fu Chien,et al.  Yield improvement planning for the recycle processes of test wafers , 2006 .

[7]  Chung Kwan Shin,et al.  A machine learning approach to yield management in semiconductor manufacturing , 2000 .

[8]  Young Hoon Lee,et al.  Daily planning and scheduling system for the EDS process in a semiconductor manufacturing facility , 2009 .

[9]  A. Singh,et al.  Random defect limited yield using a deterministic model , 2001, Proceedings of the Fourteenth Biennial University/Government/Industry Microelectronics Symposium (Cat. No.01CH37197).

[10]  Wen-Chih Wang,et al.  Data mining for yield enhancement in semiconductor manufacturing and an empirical study , 2007, Expert Syst. Appl..

[11]  Lei Zhang,et al.  Fault tolerance mechanism in chip many-core processors , 2007 .

[12]  Cl Huang,et al.  The construction of production performance prediction system for semiconductor manufacturing with artificial neural networks , 1999 .

[13]  J. Choma.  The computation of semiconductor sheet resistance , 1985, IEEE Transactions on Electron Devices.

[14]  Armin Shmilovici,et al.  Data mining for improving a cleaning process in the semiconductor industry , 2002 .

[15]  Wolfgang Rosenstiel,et al.  Error Classification and Yield Prediction of Chips in Semiconductor Industry Applications , 2000, Neural Computing & Applications.

[16]  Patrick J. McNally,et al.  Integrated circuit process control monitoring (PCM) data and wafer yield analysed by using synchrotron x-ray topographic measurements , 2003 .

[17]  Fei-Long Chen,et al.  A neural-network approach to recognize defect spatial pattern in semiconductor fabrication , 2000 .

[18]  G. A. Allan,et al.  Targeted layout modifications for semiconductor yield/reliability enhancement , 2004, IEEE Transactions on Semiconductor Manufacturing.

[19]  Koichi Sakurai,et al.  A new accurate yield prediction method for system-LSI embedded memories , 2003 .

[20]  Costas J. Spanos,et al.  Semiconductor yield improvement: results and best practices , 1995 .

[21]  Charles Weber.  Yield learning and the sources of profitability in semiconductor manufacturing and process development , 2002, 13th Annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference. Advancing the Science and Technology of Semiconductor Manufacturing. ASMC 2002 (Cat. No.02CH37259).

[22]  Suk Joo Bae,et al.  Yield prediction via spatial modeling of clustered defect counts across a wafer map , 2007 .

[23]  Alissa R Sherry,et al.  Conducting and Interpreting Canonical Correlation Analysis in Personality Research: A User-Friendly Primer , 2005, Journal of personality assessment.