Embedded Implementation of Early Started Hybrid Denoising Technique for Medical Images with Optimized Loop

This paper represents the architecture of an embedded system for Early Started Hybrid Denoising Technology for Medical Images (ESHDT) using a very popular embedded processor, ATmega processor, which is inexpensive in terms of computation. Embedded implementation of the ESHDT algorithm is chosen because hardware presents a good scope of parallelism and pipelining over software. The Proposed System can work efficiently in a noisy environment. The proposed embedded system architecture has less space complexity because the number of memories is used here. The system starts performing the algorithmic task as soon as two-pixel values are received, and parallelism is achieved by the sixth level of software pipelining and two levels of dedicated hardware pipelining. Due to the design simplicity of our algorithm, it used very few memory resources. Here we used the 8-bit AVR processor which run on low power, and we optimized SD card access so we can say the power consumption by our system is low. Instead of the set of filters, simple predict and update mechanism is introduced. ESHDT provides very good-quality denoised output image with respect to PSNR, UIQI, and MSE.

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