Design of low-power, scalable-throughput systems at near/sub threshold voltage

Voltage scaling has been a prevalent method of saving energy for energy constrained applications. However, voltage scaling along with shrinking process technologies exacerbate process variation effects on transistor. Large variation in transistor parameters, result in high variation in performance and power across the chip. These effects if ignored at the stage of designing will result into unpredictable behavior when deployed in the actual field. In this paper, we leverage the benefits of voltage scaling methodology for obtaining energy efficiency and compensate for the loss in throughput by exploiting parallelism present in the various DSP designs. To achieve scalable throughput, we depend on both dynamic voltage scaling with a few operating voltage options and active unit scaling, where the number of active parallel units is reduced using power gating. We show that such hybrid method consumes 8%-77% less power compared to simple dynamic voltage scaling over different throughputs. We study this system architecture in two different workload environments, one static and one dynamic. In the former, the desired target throughput is predetermined and fixed and in the latter, it can be changed dynamically. We show that to achieve highest level of energy efficiency, the number of cores and the operating voltages vary widely between a base designs versus a process variation aware (PVA) design. We further show that the PVA design enjoys an average of 26.9% and 51.1% reduction in energy consumption for the static and dynamic designs respectively over six different DSP applications. This is because the base design needs to compensate for the effects of process variation as an after fact, while the PVA is able to make suitable decisions at the time of the design.