Rapid Industrial Prototyping and Scheduling of 3G/4G SoC Architectures with HLS Methodology

In this paper, we present a Catapult C/C++ based methodology that integrates key technologies for high-level VLSI modelling of 3G/4G wireless systems to enable extensive time/area tradeoff study. A Catapult C/C++ based architecture scheduler transfers the major workload to the algorithmic C/C++ fixed- point design. Prototyping experiences are presented to explore the VLSI design space extensively for various types of computational intensive algorithms in the HSDPA, MIMO-CDMA and MIMO- OFDM systems, such as synchronization, MIMO equalizer and the QRD-M detector. Extensive time/area tradeoff study is enabled with different architecture and resource constraints in a short design cycle. The industrial design experience demonstrates significant improvement in architecture efficiency and productiv- ity, which enables truly rapid prototyping for the 3G and beyond wireless systems.

[1]  Joseph R. Cavallaro,et al.  An Efficient Circulant MIMO Equalizer for CDMA Downlink: Algorithm and VLSI Architecture , 2006, EURASIP J. Adv. Signal Process..

[2]  GuoYuanbin,et al.  An efficient circulant MIMO equalizer for CDMA downlink , 2006 .

[3]  Markus Rupp,et al.  Prototype experience for MIMO BLAST over third-generation wireless system , 2003, IEEE J. Sel. Areas Commun..

[4]  Joseph R. Cavallaro,et al.  Rapid scheduling of efficient VLSI architectures for next-generation HSDPA wireless system using Precision C synthesizer , 2003, 14th IEEE International Workshop on Rapid Systems Prototyping, 2003. Proceedings..

[5]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[6]  Y. Guo,et al.  Compact hardware accelerator for functional verification and rapid prototyping of 4G wireless communication systems , 2004, Conference Record of the Thirty-Eighth Asilomar Conference on Signals, Systems and Computers, 2004..

[7]  Adrian Evans,et al.  Functional verification of large ASICs , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[8]  P. Nilsson,et al.  An ASIC implementation for V-BLAST Detection in 0.35 /spl mu/m CMOS , 2004, Proceedings of the Fourth IEEE International Symposium on Signal Processing and Information Technology, 2004..

[9]  Joseph R. Cavallaro,et al.  Scalable FPGA architectures for LMMSE-based SIMO chip equalizer in HSDPA downlink , 2003, The Thrity-Seventh Asilomar Conference on Signals, Systems & Computers, 2003.

[10]  J.M. Rabaey.  Low-power silicon architectures for wireless communications , 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

[11]  Giovanni De Micheli,et al.  HERCULES-a system for high-level synthesis , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..

[12]  Reinaldo A. Valenzuela,et al.  Detection algorithm and initial laboratory results using V-BLAST space-time communication architecture , 1999 .

[13]  Joseph R. Cavallaro,et al.  Efficient MIMO equalization for downlink multi-code CDMA: complexity optimization and comparative study , 2004, IEEE Global Telecommunications Conference, 2004. GLOBECOM '04..

[14]  Gerard J. Foschini,et al.  Layered space-time architecture for wireless communication in a fading environment when using multi-element antennas , 1996, Bell Labs Technical Journal.

[15]  Keshab K. Parhi,et al.  High-level DSP synthesis using concurrent transformations, scheduling, and allocation , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  Heidi Steendam,et al.  The effect of clock frequency offsets on downlink MC-DS-CDMA , 2002, IEEE Seventh International Symposium on Spread Spectrum Techniques and Applications,.

[17]  Gene H. Golub,et al.  Matrix computations , 1983 .

[18]  V. K. Jain,et al.  VLSI architecture for an advance DS/CDMA wireless communication receiver , 1997, 1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon.

[19]  Josep Vidal,et al.  Turbo linear dispersion space time coding for MIMO HSDPA systems , 2003 .

[20]  Tung-Sang Ng,et al.  Effects of carrier frequency accuracy on quasi-synchronous, multicarrier DS-CDMA communications using optimized sequences , 1999, IEEE J. Sel. Areas Commun..

[21]  Jiang Yue,et al.  Channel estimation and data detection for MIMO-OFDM systems , 2003, GLOBECOM '03. IEEE Global Telecommunications Conference (IEEE Cat. No.03CH37489).

[22]  Joseph R. Cavallaro,et al.  Advanced mimo-cdma receiver for interference suppression: algorithms, system-on-chip architectures and design methodology , 2005 .

[23]  Matti Latva-aho,et al.  Chip-Level Channel Equalization in WCDMA Downlink , 2002, EURASIP J. Adv. Signal Process..