Static Timing Analysis of Shared Caches for Multicore Processors

The state-of-the-art techniques in multicore timing analysis are limited to analyze multicores with shared instruction caches only. This paper proposes a uniform framework to analyze the worst-case performance for both shared instruction caches and data caches in a multicore platform. Our approach is based on a new concept called address flow graph, which can be used to model both instruction and data accesses for timing analysis. Our experiments, as a proof-of-concept study, indicate that the proposed approach can accurately compute the worst-case performance for real-time threads running on a dual-core processor with a shared L2 cache (either to store instructions or data). Category: Embedded computing

[1]  Tulika Mitra,et al.  Accurate estimation of cache-related preemption delay , 2003, First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721).

[2]  Microsystems Sun,et al.  Jini^ Architecture Specification Version 2.0 , 2003 .

[3]  Byoung-Do Kim,et al.  Computational Methods for On-Node Performance Optimization and Inter-Node Scalability of HPC Applications , 2012, J. Comput. Sci. Eng..

[4]  Chang-Gun Lee,et al.  Bounding Cache-Related Preemption Delay for Real-Time Systems , 2001, IEEE Trans. Software Eng..

[5]  Greger Ottosson,et al.  Worst-case execution time analysis for modern hardware architectures , 1997 .

[6]  Syed S. Rizvi.  Algorithm for Improving the Computing Power of Next Generation Wireless Receivers , 2012, J. Comput. Sci. Eng..

[7]  Wei Zhang,et al.  Accurately Estimating Worst-Case Execution Time for Multi-core Processors with Shared Direct-Mapped Instruction Caches , 2009, 2009 15th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications.

[8]  Wei Zhang,et al.  WCET Analysis for Multi-Core Processors with Shared L2 Instruction Caches , 2008, 2008 IEEE Real-Time and Embedded Technology and Applications Symposium.

[9]  Jakob Engblom,et al.  The worst-case execution-time problem—overview of methods and survey of tools , 2008, TECS.

[10]  James H. Anderson,et al.  Real-Time Scheduling on Multicore Platforms , 2006, 12th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'06).

[11]  Jakob Engblom,et al.  Efficient longest executable path search for programs with complex flows and pipeline effects , 2001, CASES '01.

[12]  James H. Anderson,et al.  A Hybrid Real-Time Scheduling Approach for Large-Scale Multicore Platforms , 2007, 19th Euromicro Conference on Real-Time Systems (ECRTS'07).

[13]  Sharad Malik,et al.  Cache modeling for real-time software: beyond direct mapped instruction caches , 1996, 17th IEEE Real-Time Systems Symposium.

[14]  Andy J. Wellings,et al.  Adding instruction cache effect to schedulability analysis of preemptive real-time systems , 1996, Proceedings Real-Time Technology and Applications.

[15]  Miodrag Potkonjak,et al.  MediaBench: a tool for evaluating and synthesizing multimedia and communications systems , 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.

[16]  Sharad Malik,et al.  Performance Analysis of Embedded Software Using Implicit Path Enumeration , 1995, 32nd Design Automation Conference.

[17]  B. R. Rau,et al.  HPL-PD Architecture Specification:Version 1.1 , 2000 .

[18]  David B. Whalley,et al.  Integrating the timing analysis of pipelining and instruction caching , 1995, Proceedings 16th IEEE Real-Time Systems Symposium.

[19]  Sang Lyul Min,et al.  Analysis of cache-related preemption delay in fixed-priority preemptive scheduling , 1998, 17th IEEE Real-Time Systems Symposium.

[20]  Yun Liang,et al.  Timing Analysis of Concurrent Programs Running on Shared Cache Multi-Cores , 2009, RTSS.

[21]  Damien Hardy,et al.  WCET Analysis of Multi-level Non-inclusive Set-Associative Instruction Caches , 2008, 2008 Real-Time Systems Symposium.