Variation-Aware Structural Synthesis of Analog Circuits via Hierarchical Building Blocks and Structural Homotopy

This paper presents MOJITO-R, a tool that performs variation-aware structural synthesis of analog circuits. It returns trustworthy topologies by searching across a space of thousands of possible topologies defined by hierarchically organized analog structural building blocks. ldquoStructural homotopyrdquo conducts search at several objective-function tightening levels (numbers of process corners) simultaneously. Multiobjective evolutionary search returns sized topologies which trade off power, area, performances, and yield. An experimental validation run returned 78 643 Pareto-optimal designs, having 982 sized topologies with various specification/yield combinations. A decision tree is extracted to visualize the performance-topology relationship.

[1]  John R. Koza,et al.  Automated synthesis of analog electrical circuits by means of genetic programming , 1997, IEEE Trans. Evol. Comput..

[2]  Alex Doboli,et al.  Exploration-based high-level synthesis of linear analog systems operating at low/medium frequencies , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Georges G. E. Gielen,et al.  WATSON: design space boundary exploration and model generation for analog and RFIC design , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  Jianjun Hu,et al.  Robust and Efficient Genetic Algorithms with Hierarchical Niching and a Sustainable Evolutionary Computation Model , 2004, GECCO.

[5]  Alex Doboli,et al.  High-level synthesis of /spl Delta//spl Sigma/ Modulator topologies optimized for complexity, sensitivity, and power consumption , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Georges Gielen,et al.  A Computer-Aided Design and Synthesis Environment for Analog Integrated Circuits , 2002 .

[7]  Jason D. Lohn,et al.  Automated Analog Circuit Sythesis Using a Linear Representation , 1998, ICES.

[8]  Kalyanmoy Deb,et al.  A fast and elitist multiobjective genetic algorithm: NSGA-II , 2002, IEEE Trans. Evol. Comput..

[9]  P.R. Gray,et al.  OPASYN: a compiler for CMOS operational amplifiers , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  John R. Koza,et al.  Genetic programming - on the programming of computers by means of natural selection , 1993, Complex adaptive systems.

[11]  John R. Koza,et al.  Genetic Programming III: Darwinian Invention & Problem Solving , 1999 .

[12]  Christofer Toumazou,et al.  The invention of CMOS amplifiers using genetic programming and current-flow analysis , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  Wei-Yin Loh,et al.  Classification and regression trees , 2011, WIREs Data Mining Knowl. Discov..

[14]  Domine Leenaerts,et al.  DARWIN: CMOS opamp Synthesis by Means of a Genetic Algorithm , 1995, 32nd Design Automation Conference.

[15]  Dario Floreano,et al.  Analog Genetic Encoding for the Evolution of Circuits and Networks , 2007, IEEE Transactions on Evolutionary Computation.

[16]  Trent McConaghy,et al.  Importance sampled circuit learning ensembles for robust analog IC design , 2008, ICCAD 2008.

[17]  Willy Sansen,et al.  HECTOR: a hierarchical topology-construction program for analog circuits based on a declarative approach to circuit modeling , 1991, Proceedings of the IEEE 1991 Custom Integrated Circuits Conference.

[18]  Xin Yao,et al.  Evolutionary programming made faster , 1999, IEEE Trans. Evol. Comput..

[19]  Xiaoying Wang,et al.  An approach to topology synthesis of analog circuits using hierarchical blocks and symbolic analysis , 2006, Asia and South Pacific Conference on Design Automation, 2006..

[20]  C.C. McAndrew,et al.  A comprehensive MOSFET mismatch model , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[21]  John R. Koza,et al.  Genetic Programming IV: Routine Human-Competitive Machine Intelligence , 2003 .

[22]  K. Francken,et al.  DAISY: a simulation-based high-level synthesis tool for /spl Delta//spl Sigma/ modulators , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[23]  Michiel Steyaert,et al.  An Efficient Methodology for Hierarchical Synthesis of Mixed-Signal Systems with Fully Integrated Building Block Topology Selection , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[24]  Hitoshi Iba,et al.  Evolving analog circuits by variable length chromosomes , 2003 .

[25]  Michiel Steyaert,et al.  Simultaneous Multi-Topology Multi-Objective Sizing Across Thousands of Analog Circuit Topologies , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[26]  Franz Rothlauf,et al.  Representations for genetic and evolutionary algorithms , 2002, Studies in Fuzziness and Soft Computing.

[27]  Nobuo Fujii,et al.  Automated design of analog circuits using cell-based structure , 2002, Proceedings 2002 NASA/DoD Conference on Evolvable Hardware.

[28]  Stephen J. Wright,et al.  Numerical Optimization , 2018, Fundamental Statistical Inference.

[29]  Ranga Vemuri,et al.  Topology synthesis of analog circuits based on adaptively generated building blocks , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[30]  Willy Sansen,et al.  analog design essentials , 2011 .

[31]  Ricardo Salem Zebulum,et al.  Evolutionary Electronics , 2001 .

[32]  Peng Li,et al.  Yield-aware analog integrated circuit optimization using geostatistics motivated performance modeling , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[33]  Rob A. Rutenbar,et al.  Computer-Aided Design of Analog Integrated Circuits and Systems , 2002 .

[34]  H. Wallinga,et al.  SEAS: a simulated evolution approach for analog circuit synthesis , 1991, Proceedings of the IEEE 1991 Custom Integrated Circuits Conference.

[35]  Gregory Hornby,et al.  ALPS: the age-layered population structure for reducing the problem of premature convergence , 2006, GECCO.

[36]  Trent McConaghy,et al.  Genetic Programming in Industrial Analog CAD: Applications and Challenges , 2006 .

[37]  F. Leyn,et al.  An efficient DC root solving algorithm with guaranteed convergence for analog integrated CMOS circuits , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

[38]  Georges G. E. Gielen,et al.  Efficient multiobjective synthesis of analog circuits using hierarchical Pareto-optimal performance hypersurfaces , 2005, Design, Automation and Test in Europe.

[39]  Ulf Schlichtmann,et al.  The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[40]  Georges G. E. Gielen,et al.  HOLMES: capturing the yield-optimized design space boundaries of analog and RF integrated circuits , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[41]  Edoardo Charbon,et al.  A Top-down, Constraint-Driven Design Methodology for Analog Integrated Circuits , 1993 .

[42]  Rob A. Rutenbar,et al.  OASYS: a framework for analog circuit synthesis , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[43]  Alex Doboli,et al.  High-level Synthesis of ∆ Σ Modulator Topologies Optimized for Complexity , Sensitivity and Power Consumption , .

[44]  Georges G. E. Gielen,et al.  Performance space modeling for hierarchical synthesis of analog integrated circuits , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[45]  Michiel Steyaert,et al.  Automated extraction of expert knowledge in analog topology selection and sizing , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

[46]  Rob A. Rutenbar,et al.  Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[47]  Michiel Steyaert,et al.  Massively multi-topology sizing of analog integrated circuits , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[48]  Tatiana Kalganova,et al.  Unconstrained Evolution of Analogue Computational "QR" Circuit with Oscillating Length Representation , 2008, ICES.

[49]  Helmut Graeb,et al.  Analog Design Centering and Sizing , 2007 .

[50]  P. P. Chakrabarti,et al.  A synthesis system for analog circuits based on evolutionary search and topological reuse , 2005, IEEE Transactions on Evolutionary Computation.

[51]  W. Sansen.  Challenges in analog IC design submicron CMOS technologies , 1996, 1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings.

[52]  Franz Rothlauf,et al.  Representations for genetic and evolutionary algorithms (2. ed.) , 2006 .

[53]  J. Friedman.  Stochastic gradient boosting , 2002 .

[54]  Brian A. A. Antao,et al.  ARCHGEN: Automated synthesis of analog systems , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[55]  Nuno Horta,et al.  Algorithm-driven synthesis of data conversion architectures , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[56]  E. Berkcan,et al.  Analog compilation based on successive decompositions , 1988, DAC '88.

[57]  Rob A. Rutenbar,et al.  Integer programming based topology selection of cell-level analog circuits , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[58]  Christofer Toumazou,et al.  ISAID-a methodology for automated analog IC design , 1990, IEEE International Symposium on Circuits and Systems.

[59]  Ieee Circuits,et al.  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems information for authors , 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[60]  Nikolaus Hansen,et al.  A restart CMA evolution strategy with increasing population size , 2005, 2005 IEEE Congress on Evolutionary Computation.