Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC

Capacitor-couple technique used to lower snapback-trigger voltage and to ensure uniform ESD current distribution in deep-submicron CMOS on-chip ESD protection circuit is proposed. The coupling capacitor is realized by a poly layer right under the wire-bonding metal pad without increasing extra layout area to the pad. A timing-original design model has been derived to calculate the capacitor-couple efficiency of this proposed ESD protection circuit. Using this capacitor-couple ESD protection circuit, the thinner gate oxide of CMOS devices in deep-submicron low-voltage CMOS ASIC can be effectively protected.

[2]  Kueing-Long Chen.  The effects of interconnect process and snapback voltage on the ESD failure threshold of NMOS transistors , 1988 .

[3]  Chung-Yu Wu,et al.  Modeling the positive-feedback regenerative process of CMOS latchup by a positive transient pole method. I. theoretical derivation , 1995 .

[4]  C. Duvvury,et al.  ESD: a pervasive reliability concern for IC technologies , 1993 .

[5]  R. Muller,et al.  VIA-4 avalanche-induced breakdown mechanisms in short-channel MOSFETs , 1982, IEEE Transactions on Electron Devices.

[6]  Ming-Dou Ker,et al.  Area-efficient CMOS output buffer with enhanced high ESD reliability for deep submicron CMOS ASIC , 1995, Proceedings of Eighth International Application Specific Integrated Circuits Conference.

[7]  C. Hu,et al.  High-current snapback characteristics of MOSFETs , 1990 .

[8]  Chenming Hu,et al.  An analytical breakdown model for short-channel MOSFET's , 1982, IEEE Transactions on Electron Devices.

[9]  Chung-Yu Wu,et al.  An Efficient Timing Model for CMOS Combinational Logic Gates , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  Wolfgang Nikutta,et al.  Influence of the series resistance of on-chip power supply buses on internal device failure after ESD stress (MOS devices) , 1993 .

[11]  Sung-Mo Kang,et al.  EOS/ESD reliability of deep sub-micron NMOS protection devices , 1995, Proceedings of 1995 IEEE International Reliability Physics Symposium.

[12]  C. Duvvury,et al.  Dynamic gate coupling of NMOS for efficient output ESD protection , 1992, 30th Annual Proceedings Reliability Physics 1992.

[13]  T. Polgreen,et al.  A low-voltage triggering SCR for on-chip ESD protection at output and input pads , 1990, IEEE Electron Device Letters.

[14]  Chung-Yu Wu,et al.  Complementary-LVTSCR ESD protection scheme for submicron CMOS IC's , 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

[15]  R. N. Rountree,et al.  Internal chip ESD phenomena beyond the protection circuit , 1988 .

[16]  C.H. Diaz,et al.  Building-in ESD/EOS reliability for sub-halfmicron CMOS processes , 1995, Proceedings of 1995 IEEE International Reliability Physics Symposium.

[17]  C. Duvvury,et al.  Achieving uniform nMOS device power distribution for sub-micron ESD reliability , 1992, 1992 International Technical Digest on Electron Devices Meeting.

[18]  C. Duvvury,et al.  The impact of technology scaling on ESD robustness and protection circuit design , 1995 .