High Level Simulation Directed RTL Power Estimation

In this chapter, we present a high-level power estimation methodology, which is based on a high-level synthesis framework and supports sufficiently accurate power estimation of hardware designs at the high-level. For early and accurate power estimation, the proposed methodology utilizes RTL probabilistic power estimation technique controlled by the high-level simulation. Furthermore, our methodology does not require a designer to move to the traditional RTL power estimation methodology, thus facilitating easy and early power analysis and aiding the cause of adoption of high-level design practices in ASIC design flow. This chapter provides detailed description of our methodology including tools used, algorithm for extracting activity from high-level value change dump and finally mapping this information for RTL power estimation.